XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 33

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 18: Dual-Port RAM Function
Table 19: Distributed RAM Signals
DS312-2 (v3.4) November 9, 2006
Product Specification
Notes:
1.
2.
WE (mode)
WCLK
WE
1 (write)
0 (read)
1 (read)
1 (read)
1 (read)
data_a = word addressed by bits A3-A0.
data_d = word addressed by bits DPRA3-DPRA0.
Signal
Figure 27: Dual-Port RAM Component
R
Inputs
WCLK
DPRA0
DPRA1
DPRA2
DPRA3
WCLK
↑
X
0
1
The clock is used for synchronous
writes. The data and the address input
pins have setup times referenced to the
WCLK pin. Active on the positive edge
by default with built-in programmable
polarity.
functionality of the port. An inactive
Write Enable prevents any writing to
memory cells. An active Write Enable
causes the clock edge to write the data
input signal to the memory location
pointed to by the address inputs. Active
High by default with built-in
programmable polarity.
↓
The enable pin affects the write
WE
A0
A1
A2
A3
D
RAM16X1D
D
X
X
X
D
X
DS312-2_42_021305
Description
SPO
DPO
data_a
data_a
data_a
data_a
SPO
D
Outputs
data_d
data_d
data_d
data_d
data_d
DPO
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Table 19: Distributed RAM Signals (Continued)
The INIT attribute can be used to preload the memory with
data during FPGA configuration. The default initial contents
for RAM is all zeros. If the WE is held Low, the element can
be considered a ROM. The ROM function is possible even
in the SLICEL.
The global write enable signal, GWE, is asserted automati-
cally at the end of device configuration to enable all writable
elements. The GWE signal guarantees that the initialized
distributed RAM contents are not disturbed during the con-
figuration process.
The distributed RAM is useful for smaller amounts of mem-
ory. Larger memory requirements can use the dedicated
18Kbit RAM blocks (see
For more information on distributed RAM, see XAPP464:
Using Look-Up Tables as Distributed RAM in Spartan-3
FPGAs.
Shift Registers
It is possible to program each SLICEM LUT as a 16-bit shift
register (see
delay serial data anywhere from 1 to 16 clock cycles without
using any of the dedicated flip-flops. The resulting program-
mable delays can be used to balance the timing of data
pipelines.
The SLICEM LUTs cascade from the G-LUT to the F-LUT
through the DIFMUX (see
SHIFTOUT lines cascade a SLICEM to the SLICEM below
to form larger shift registers. The four SLICEM LUTs of a
single CLB can be combined to produce delays up to 64
clock cycles. It is also possible to combine shift registers
across more than one CLB.
A0, A1, A2, A3
(A4, A5)
D
O, SPO, and
DPO
Signal
Figure
The address inputs select the memory
cells for read or write. The width of the
port determines the required address
inputs.
The data input provides the new data
value to be written into the RAM.
The data output O on single-port RAM
or the SPO and DPO outputs on
dual-port RAM reflects the contents of
the memory cells referenced by the
address inputs. Following an active
write clock edge, the data out (O or
SPO) reflects the newly written data.
28). Used in this way, each LUT can
Block
RAM).
Figure
Description
Functional Description
15). SHIFTIN and
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