XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 108

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain,
forcing the FPGAs to start synchronously. Similarly, the
start-up sequence can be paused at any stage, waiting for
selected DCMs to lock to their respective input clock sig-
nals. See also
Mode.
By default, the start-up sequence is synchronized to CCLK.
Alternatively, the start-up sequence can be synchronized to
a user-specified clock from within the FPGA application
using the
setting the
FPGA application can optionally assert the GSR and GTS
signals via the STARTUP_SPARTAN3E primitive. For
JTAG configuration, the start-up sequence can be synchro-
nized to the TCK clock input.
Readback
FPGA configuration data can be read back using either the
Slave Parallel or JTAG mode. This function is disabled if the
Bitstream Generator
or Level2.
Along with the configuration data, it is possible to read back
the contents of all registers and distributed RAM.
To synchronously control when register values are captured
for readback, use the
tive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
The Readback feature is available in most Spartan-3E
FPGA product options, as indicated in
back feature is not available in the XC3S1200E and
XC3S1600E FPGAs when using the -4 speed grade in the
Commercial temperature grade. Similarly, block RAM
Readback support is not available in the -4 speed grade,
Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options
108
ConfigRate
StartupClk
Option Name
STARTUP_SPARTAN3E
StartupClk
Stabilizing DCM Clocks Before User
Pins/Function
Configuration,
Configuration
Affected
Startup
Security
CCLK,
CAPTURE_SPARTAN3
bitstream generator option. The
option is set to either Level1
12, 25, 50
(default)
UserClk
Values
1, 3, 6,
library primitive and by
Cclk
Jtag
Table
67. The Read-
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency, and the new setting is loaded as part of the configuration bitstream. The
software default value is 1 (~1.5 MHz) starting with ISE 8.1, Service Pack 1.
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up.
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up. The
FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
The JTAG TCK input controls the startup sequence when the FPGA transitions from
the configuration mode to the user mode. See Start-Up.
library primi-
www.xilinx.com
Commercial temperature devices. If Readback is required
in an XC3S1200E or XC3S1600E FPGA, or if block RAM
Readback is required on any Spartan-3E FPGA, upgrade to
either the Industrial temperature grade version or the -5
speed grade.
The Xilinx iMPACT programming software uses the Read-
back feature for its optional Verify and Readback opera-
tions. The Xilinx ChipScope™ software presently does not
use Readback but may in future updates.
Table 67: Readback Support in Spartan-3E FPGAs
Bitstream Generator (BitGen) Options
Various Spartan-3E FPGA functions are controlled by spe-
cific bits in the configuration bitstream image. These values
are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
Table 68
FPGAs.
Block RAM Readback
General Readback (registers, distributed RAM)
Temperature Range
All Spartan-3E
Speed Grade
provides a list of all BitGen options for Spartan-3E
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
Description
FPGAs
Yes
Yes
Yes
No
No
No
DS312-2 (v3.4) November 9, 2006
-4
Commercial
Product Specification
Yes
Yes
Yes
Yes
Yes
Yes
-5
Industrial
Yes
Yes
Yes
Yes
Yes
Yes
-4
R