XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 211

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

User I/Os by Bank
Table 148
pins are distributed between the four I/O banks on the
FG320 package.
Table 148: User I/Os Per Bank for XC3S500E in the FG320 Package
Table 149: User I/Os Per Bank for XC3S1200E and XC3S1600E in the FG320 Package
DS312-4 (v3.4) November 9, 2006
Product Specification
Notes:
1.
Notes:
1.
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
Edge
and
R
Table 149
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
indicate how the available user-I/O
Maximum
Maximum
232
250
I/O
I/O
58
58
58
58
61
63
63
63
102
120
I/O
I/O
29
22
17
34
34
25
23
38
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INPUT
INPUT
14
10
13
11
48
12
12
11
12
47
All Possible I/O Pins by Type
All Possible I/O Pins by Type
DUAL
DUAL
21
24
46
21
24
46
1
0
1
0
VREF
VREF
20
21
6
5
4
5
6
5
5
5
Pinout Descriptions
CLK
CLK
0
0
0
0
16
16
8
8
(1)
(1)
8
8
(1)
(1)
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