XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 38

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Block RAM Port Signal Definitions
38
Caution!
RAMB16_S[w
RAMB16_S[w] with their associated signals are shown in
Figure 32a
defined in
SSR) on the block RAM are active High. However, optional
Notes:
1.
2.
3.
4.
DIA[w
DIB[w
ADDRA[r
ADDRB[r
DIPB[p
DIPA[p
w
p
r
The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
A
A
A
and r
A
B
and p
and w
–p
–p
Table
Representations of the dual-port primitive
and
SSRA
A
A
A
SSRB
B
B
B
CLKA
CLKB
B
WEA
WEB
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
A
ENA
ENB
B
B
are integers representing the address bus width at ports A and B, respectively.
]_S[w
Figure
are integers that indicate the number of data path lines serving as parity bits.
23. The control signals (WE, EN, CLK, and
are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
B
] and the single-port primitive
32b, respectively. These signals are
RAMB16_S
(a) Dual-Port
W A
_S
W B
Figure 32: Block RAM Primitives
DOPA[p
DOA[w
DOPB[p
DOB[w
A
B
A
–p
B
–p
www.xilinx.com
–1:0]
–1:0]
A
B
–1:0]
–1:0]
inverters on the control signals change the polarity of the
active edge to active Low.
!
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
Whenever a block RAM port is enabled (ENA or ENB
= High), all address transitions must meet the data
sheet setup and hold times with respect to the port
clock (CLKA or CLKB), as shown in
page
RAM read output is of no interest.
SSR
CLK
WE
142.This requirement must be met even if the
EN
(b) Single-Port
DESIGN NOTE:
RAMB16_Sw
DS312-2 (v3.4) November 9, 2006
Product Specification
DOP[p–1:0]
DO[w–p–1:0]
Table 102,
DS312-2_03_111105
R