XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 79

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 53: Example SPI Flash PROM Connections and Pin Naming
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
enable pull-up resistors on all user-I/O pins or High to dis-
DS312-2 (v3.4) November 9, 2006
Product Specification
DATA_IN
DATA_OUT
SELECT
CLOCK
WR_PROTECT
HOLD
(see
RESET
(see
RDY/BUSY
(see
P
SPI Flash Pin
Similarly, the FPGA’s HSWAP pin must be Low to
Figure
Figure
Figure
W
R
53)
54)
54)
MOSI
DIN
CSO_B
CCLK
Not required for FPGA configuration. Must be
High to program SPI Flash. Optional
connection to FPGA user I/O after
configuration.
Not required for FPGA configuration but must
be High during configuration. Optional
connection to FPGA user I/O after
configuration. Not applicable to Atmel
DataFlash.
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
FPGA Connection
www.xilinx.com
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
STMicro
HOLD
N/A
N/A
W
Q
D
S
C
NexFlash
HOLD
CLK
WP
N/A
N/A
DO
CS
DI
Technology
Storage
Silicon
HOLD#
WP#
SCK
CE#
N/A
N/A
SO
Functional Description
SI
RDY/BUSY
DataFlash
RESET
Atmel
SCK
N/A
WP
SO
CS
SI
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