XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 82

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other V
V
If the FPGA's V
valid, then the FPGA waits for VCCO_2 to reach its mini-
mum threshold voltage before starting configuration. This
threshold voltage is labeled as V
ule 3 and ranges from approximately 0.4V to 1.0V, substan-
tially lower than the SPI Flash PROM's minimum voltage.
Once all three FPGA supplies reach their respective Power
On Reset (POR) thresholds, the FPGA starts the configura-
tion process and begins initializing its internal configuration
memory. Initialization requires approximately 1 ms (T
minimum in
de-asserts INIT_B, selects the SPI Flash PROM, and starts
sending the appropriate read command. The SPI Flash
PROM must be ready for read operations at this time. Spar-
tan-3E FPGAs issue the read command just once. If the SPI
Flash is not ready, then the FPGA does not properly config-
ure.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time. Alter-
nately, a Power Good signal from the 3.3V supply or a sys-
tem reset signal accomplishes the same purpose. Use an
open-drain or open-collector output when driving PROG_B
or INIT_B.
SPI Flash PROM Density Requirements
Table 56
program a single Spartan-3E FPGA. Commercially avail-
able SPI Flash PROMs range in density from 1 Mbit to 128
Mbits. A multiple-FPGA daisy-chained application requires
82
CCAUX
supplies, and consequently, there is no issue. How-
Figure 55: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
shows the smallest usable SPI Flash PROM to
Table 110
FPGA VCCO_2 minimum
Power On Reset Voltage
CCINT
(V
SPI Flash PROM
minimum voltage
of Module 3, after which the FPGA
and V
CCINT
already valid)
, V
CCAUX
(V
CCAUX
CCO2T
CCO2T
3.3V Supply
Figure
supplies are already
)
in
Table 73
54. Release the
SPI Flash cannot be selected
CCINT
FPGA initializes configuration
of Mod-
www.xilinx.com
POR
and
memory
,
ever, if the 3.3V supply feeding the FPGA's VCCO_2 supply
is last in the sequence, a potential race occurs between the
FPGA and the SPI Flash PROM, as shown in
PROM CS
a SPI Flash PROM large enough to contain the sum of the
FPGA file sizes. An application can also use a larger-den-
sity SPI Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the SPI Flash
PROM can also store application code for a MicroBlaze™
RISC processor core integrated in the Spartan-3E FPGA.
See
Table 56: Number of Bits to Program a Spartan-3E
FPGA and Smallest SPI Flash PROM
CCLK Frequency
In SPI Flash mode, the FPGA’s internal oscillator generates
the configuration clock frequency. The FPGA provides this
clock on its CCLK output pin, driving the PROM’s clock
input pin. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate
quency supported by the FPGA configuration logic depends
on the timing for the SPI Flash device. Without examining
the timing for a specific SPI Flash PROM, use
delay
SPI Flash
(T
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
POR
Using the SPI Flash Interface after
Device
(t
Time
)
VSL
)
bitstream generator option. The maximum fre-
SPI Flash available for
read operations
SPI Flash PROM
FPGA accesses
Configuration
access, otherwise delay
SPI Flash PROM must
Number of
FPGA configuration
1,353,728
2,270,208
3,841,184
5,969,696
be ready for FPGA
581,344
Bits
DS312-2 (v3.4) November 9, 2006
DS312-2_50b_110206
Product Specification
SPI Flash PROM
Smallest Usable
Configuration.
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
Figure
55.
R