XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 158

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

DC and Switching Characteristics
IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 122: Timing for the JTAG Test Access Port
158
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
F
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
CCH
CCL
TCK
The numbers in this table are based on the operating conditions set forth in
Symbol
TCK
TMS
TDI
TDO
(Input)
(Input)
(Input)
(Output)
The time from the falling transition on the TCK pin
to data appearing at the TDO pin
The time from the setup of data at the TDI pin to
the rising transition at the TCK pin
The time from the setup of a logic level at the TMS
pin to the rising transition at the TCK pin
The time from the rising transition at the TCK pin
to the point when data is last held at the TDI pin
The time from the rising transition at the TCK pin
to the point when a logic level is last held at the
TMS pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
Description
T
TDITCK
T
TMSTCK
Figure 79: JTAG Waveforms
www.xilinx.com
T
TCKTDI
T
TCKTMS
Table
76.
T
TCKTDO
Min
1.0
7.0
7.0
All Speed Grades
0
0
5
5
-
T
CCH
1/F
DS312-3 (v3.4) November 9, 2006
TCK
Max
11.0
30
-
-
-
-
-
-
T
CCL
Product Specification
DS099_06_040703
Units
MHz
ns
ns
ns
ns
ns
ns
ns
R