XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 92

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Some x8/x16 Flash PROMs have a long setup time require-
ment on the BYTE# signal. For the FPGA to configure cor-
rectly, the PROM must be in x8 mode with BYTE# = 0 at
power-on or when the FPGA’s PROG_B pin is pulsed Low.
If required, extend the BYTE# setup time for a 3.3V PROM
using an external 680 Ω pull-down resistor on the FPGA’s
LDC2 pin or by delaying assertion of the CSI_B select input
to the FPGA.
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in
<0:1:1>) for the FPGA connected to the parallel NOR Flash
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all
downstream FPGAs in the daisy-chain. If there are more
than two FPGAs in the chain, then last FPGA in the chain
can be from any Xilinx FPGA family. However, all interme-
diate FPGAs located in the chain between the first and last
FPGAs must from either the Spartan-3E or Virtex™-5
FPGA families.
After the master FPGA—the FPGA on the left in the dia-
gram—finishes loading its configuration data from the paral-
lel Flash PROM, the master device continues generating
addresses to the Flash PROM and asserts its CSO_B out-
put Low, enabling the next FPGA in the daisy-chain. The
next FPGA then receives parallel configuration data from
the Flash PROM. The master FPGA’s CCLK output syn-
chronizes data capture.
If HSWAP = 1, an external 4.7kΩ pull-up resistor must be
added on the CSO_B pin. If HSWAP = 0, no external pull-up
is necessary.
BPI Mode Interaction with Right and Bottom Edge
Global Clock Inputs
Some of the BPI mode configuration pins are shared with
global clock inputs along the right and bottom edges of the
92
!
BPI mode daisy chain software support is available
starting in ISE 8.2i.
Answer Record #23061
www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath
=23061
Also, in a multi-FPGA daisy-chain configuration of
more than two devices, all intermediate FPGAs
between the first and last devices must be Spartan-3E
or Virtex-5 FPGAs. The last FPGA in the chain can be
from any Xilinx FPGA family.
Figure
59. Use BPI mode (M[2:0] = <0:1:0> or
DESIGN NOTE:
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device (Bank 1 and Bank 2, respectively). These pins are
not easily reclaimable for clock inputs after configuration,
especially if the FPGA application access the parallel NOR
Flash after configuration.
pins.
Table 63: Shared BPI Configuration Mode and Global
Buffer Input Pins
Stepping 0 Limitations when Reprogramming via
JTAG if FPGA Set for BPI Configuration
The FPGA can always be reprogrammed via the JTAG port,
regardless of the mode pin (M[2:0]) settings. However,
Stepping 0 devices have a minor limitation. If a Stepping 0
FPGA is set to configure in BPI mode and the FPGA is
attached to a parallel memory containing a valid FPGA con-
figuration file, then subsequent reconfigurations using the
JTAG port will fail. Potential workarounds include setting the
mode pins for JTAG configuration (M[2:0] = <1:0:1>) or off-
setting the initial memory location in Flash by 0x2000.
Stepping 1 and later devices fully support JTAG configura-
tion even when the FPGA mode pins are set for BPI mode.
Device
Bottom
Edge
Right
Global Buffer
Input Pin
GCLK12
GCLK13
GCLK14
GCLK15
RHCLK0
RHCLK1
RHCLK2
RHCLK3
RHCLK4
RHCLK5
RHCLK6
RHCLK7
GCLK0
GCLK2
GCLK3
Table 63
DS312-2 (v3.4) November 9, 2006
summarizes the shared
Configuration Pin
Product Specification
BPI Mode
RDWR_B
A10
D2
D1
D7
D6
D4
D3
A9
A8
A7
A6
A5
A4
A3
R