XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 110

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
110
ProgPin
TckPin
TdiPin
TdoPin
TmsPin
UserID
Security
CRC
Persist
Option Name
Pins/Function
reconfiguration
JTAG TCK pin
JTAG TDO pin
JTAG TMS pin
interface pins,
JTAG User ID
JTAG TDI pin
Configuration
Configuration
PROG_B pin
Slave mode,
SelectMAP,
SelectMAP
Readback,
BPI mode,
Affected
register
Partial
JTAG,
(default)
Pulldown
Pulldown
Pulldown
Pulldown
Pullnone
Pullnone
Pullnone
Pullnone
Pullnone
Enable
Disable
Values
Pullup
Pullup
Pullup
Pullup
Pullup
Level1
Level2
string
None
User
Yes
No
Internally connects a pull-up resistor or between PROG_B pin and V
external 4.7 kΩ pull-up resistor to V
No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
V
Internally connects a pull-up resistor between JTAG TCK pin and V
Internally connects a pull-down resistor between JTAG TCK pin and GND.
No internal pull-up resistor on JTAG TCK pin.
Internally connects a pull-up resistor between JTAG TDI pin and V
Internally connects a pull-down resistor between JTAG TDI pin and GND.
No internal pull-up resistor on JTAG TDI pin.
Internally connects a pull-up resistor between JTAG TDO pin and V
Internally connects a pull-down resistor between JTAG TDO pin and GND.
No internal pull-up resistor on JTAG TDO pin.
Internally connects a pull-up resistor between JTAG TMS pin and V
Internally connects a pull-down resistor between JTAG TMS pin and GND.
No internal pull-up resistor on JTAG TMS pin.
The 32-bit JTAG User ID register value is loaded during configuration. The default
value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
Readback and limited partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Limited partial reconfiguration is still available via the
JTAG port or via the SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Limited partial reconfiguration is disabled.
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Turn off CRC checking.
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see
configuration and are not available as user-I/O.
CCAUX
is required.
www.xilinx.com
CCAUX
Description
is still recommended.
Slave Parallel
DS312-2 (v3.4) November 9, 2006
Mode) are reserved after
Product Specification
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
.
.
.
.
. An
R