XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 90

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Table 59: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Compatible Flash Families
The Spartan-3E BPI configuration interface operates with a
wide variety of x8 or x8/x16 parallel NOR Flash devices.
Table 60
with the Spartan-3E BPI interface. Consult the data sheet
for the desired parallel NOR Flash to determine its suitabil-
ity The basic timing requirements and waveforms are pro-
vided in
Timing
Table 60: Compatible Parallel NOR Flash Families
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate
Table 61: Maximum ConfigRate Settings for Parallel
Flash PROMs (Commercial Temperature Range)
Table 61
ous PROM read access times over the Commercial temper-
90
ST Microelectronics
Atmel
Spansion
Intel
Macronix
Flash Read Access Time
Spartan-3E FPGA
XC3S1200E
XC3S1600E
XC3S100E
XC3S250E
XC3S500E
Flash Vendor
(Module 3).
provides a few Flash memory families that operate
shows the maximum ConfigRate settings for vari-
Byte Peripheral Interface (BPI) Configuration
< 250 ns
< 115 ns
(AMD, Fujitsu)
< 45 ns
bitstream generator option.
Uncompressed
File Sizes (bits)
Flash Memory Family
Maximum ConfigRate
1,353,728
2,270,208
3,841,184
5,969,696
581,344
J3D StrataFlash
AT29 / AT49
Am29 / S29
M29W
Setting
MX29
12
3
6
www.xilinx.com
Parallel Flash PROM
ature operating range. See
Configuration Timing
mation. Despite using slower ConfigRate settings, BPI
mode is equally fast as the other configuration modes. In
BPI mode, data is accessed at the ConfigRate frequency
and internally serialized with an 8X clock frequency.
Using the BPI Interface after Configuration
After the FPGA successfully completes configuration, all
pins connected to the parallel Flash PROM are available as
user I/Os.
If not using the parallel Flash PROM after configuration,
drive LDC0 High to disable the PROM’s chip-select input.
The remainder of the BPI pins then become available to the
FPGA application, including all 24 address lines, the eight
data lines, and the LDC2, LDC1, and HDC control pins.
Because all the interface pins are user I/Os after configura-
tion, the FPGA application can continue to use the interface
pins to communicate with the parallel Flash PROM. Parallel
Flash PROMs are available in densities ranging from 1 Mbit
up to 128 Mbits and beyond. However, a single Spartan-3E
FPGA requires less than 6 Mbits for configuration. If
desired, use a larger parallel Flash PROM to contain addi-
tional non-volatile application data, such as MicroBlaze pro-
cessor code, or other user data, such as serial numbers and
Ethernet MAC IDs. In such an example, the FPGA config-
ures from parallel Flash PROM. Then using FPGA logic
after configuration, a MicroBlaze processor embedded
within the FPGA can either execute code directly from par-
allel Flash PROM or copy the code to external DDR
SDRAM and execute from DDR SDRAM. Similarly, the
FPGA application can store non-volatile application data
within the parallel Flash PROM.
The FPGA configuration data is stored starting at either at
location 0 or the top of memory (addresses all ones) or at
both locations for MultiBoot mode. Store any additional data
beginning in other available parallel Flash PROM sectors.
Do not mix configuration data and user data in the same
sector.
Similarly, the parallel Flash PROM interface can be
expanded to additional parallel peripherals.
Smallest Usable
1 Mbit
2 Mbit
4 Mbit
4 Mbit
8 Mbit
(Module 3) for more detailed infor-
Byte Peripheral Interface (BPI)
DS312-2 (v3.4) November 9, 2006
Minimum Required
Address Lines
Product Specification
A[16:0]
A[17:0]
A[18:0]
A[18:0]
A[19:0]
R