XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 84

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in
Programming Support
For successful daisy-chaining, the DONE_cycle configura-
tion option must be set to cycle 5 or sooner. The default
cycle is 4. See
tional information.
ally pre-programmed before it is mounted on the printed cir-
cuit board. The
industry-standard programming files that can be used with
third-party gang programmers. Consult your specific SPI
Flash vendor for recommended production programming
solutions.
In-system programming support is available from some
third-party PROM programmers using a socket adapter with
attached wires. To gain access to the SPI Flash signals,
84
I
Recommend
open-drain
In production applications, the SPI Flash PROM is usu-
PROG_B
!
driver
TMS
TDO
TCK
TDI
+2.5V
JTAG
SPI mode daisy chains are supported only in
Stepping 1 and later silicon versions.
Variant Select
Figure
Table 68
SPI Mode
Xilinx ISE development software
S
‘0’
‘0’
‘1’
‘1’
‘1’
P
57. Daisy-chaining from a single SPI
Figure 57: Daisy-Chaining from SPI Flash Mode (Stepping 1 and Later)
!
HSWAP
M2
M1
M0
VS2
VS1
VS0
TDI
TMS
TCK
PROG_B
and the
DESIGN NOTE:
SPI-based daisy-chaining is
only supported in Stepping 1.
Spartan-3E
VCCINT
FPGA
+1.2V
GND
Start-Up
VCCAUX
VCCO_0
VCCO_2
CSO_B
INIT_B
DONE
DOUT
CCLK
MOSI
TDO
DIN
section for addi-
VCCO_0
+3.3V
+2.5V
produces
I
www.xilinx.com
W
‘1’
P
+2.5V
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
serial Flash PROM is supported in Stepping 1 and later
devices. It is not supported in Stepping 0 devices. Use SPI
Flash mode (M[2:0] = <0:0:1>) for the FPGA connected to
the Platform Flash PROM and Slave Serial mode
(M[2:0] = <1:1:1>) for all other FPGAs in the daisy-chain.
After the master FPGA—the FPGA on the left in the dia-
gram—finishes loading its configuration data from the SPI
Flash PROM, the master device uses its DOUT output pin
to supply data to the next device in the daisy-chain, on the
falling CCLK edge.
drive the FPGA’s PROG_B input Low with an open-drain
driver. This action places all FPGA I/O pins, including those
attached to the SPI Flash, in high-impedance (Hi-Z). If the
HSWAP input is Low, the I/Os have pull-up resistors to the
V
gramming hardware then has direct access to the SPI Flash
pins. The programming access points are highlighted in the
gray box in
Beginning with the Xilinx ISE 8.2i software release, the
iMPACT programming utility provides direct, in-system pro-
totype programming support for STMicro M25P-series SPI
serial Flash PROMs and the Atmel AT45DB-series Data
Flash PROMs using the
IV, or other compatible programming cable.
+3.3V
CCO
GND
VCC
Serial
Flash
+3.3V
SPI
input on their respective I/O bank. The external pro-
Figure
Slave
Serial
Mode
P
‘1’
‘1’
‘1’
53,
HSWAP
M2
M1
M0
CCLK
DIN
TDI
PROG_B
TMS
TCK
Figure
Spartan-3E
Platform Cable
VCCINT
FPGA
+1.2V
GND
DS312-2 (v3.4) November 9, 2006
54, and
VCCAUX
VCCO_0
VCCO_2
INIT_B
DOUT
DONE
TDO
Figure
Product Specification
USB,
VCCO_0
+3.3V
+2.5V
57.
DS312-2_48_103105
Xilinx Parallel
CCLK
DOUT
PROG_B
TCK
TMS
DONE
INIT_B
R