XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 34

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Each shift register provides a shift output MC15 for the last
bit in each LUT, in addition to providing addressable access
to any bit in the shift register through the normal D output.
The address inputs A[3:0] are the same as the distributed
RAM address lines, which come from the LUT inputs F[4:1]
or G[4:1]. At the end of the shift register, the CLB flip-flop
can be used to provide one more shift delay for the addres-
sable bit.
The shift register element is known as the SRL16 (Shift
Register LUT 16-bit), with a ‘C’ added to signify a cascade
ability (Q15 output) and ‘E’ to indicate a Clock Enable. See
Figure 29
34
CE (SR)
DI (BY)
A[3:0]
SHIFTIN
CLK
Figure 28: Logic Cell SRL16 Structure
for an example of the SRLC16E component.
4
WE
CK
A[3:0]
WS
SRLC16
WSG
SHIFT-REG
MC15
DI
D
SHIFTOUT
or YB
(optional)
D
Q
X465_03_040203
Output
Registered
Output
www.xilinx.com
I
The functionality of the shift register is shown in
The SRL16 shifts on the rising edge of the clock input when
the Clock Enable control is High. This shift register cannot
be initialized either during configuration or during operation
except by shifting data into it. The clock enable and clock
inputs are shared between the two LUTs in a SLICEM. The
clock enable input is automatically kept active if unused.
Table 20: SRL16 Shift Register Function
For more information on the SRL16, refer to XAPP465:
Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3
FPGAs.
Notes:
1.
Am
Am
Am
Figure 29: SRL16 Shift Register Component with
m = 0, 1, 2, 3.
CLK
↑
X
Inputs
Cascade and Clock Enable
CE
0
1
CLK
CE
A0
A1
A2
A3
D
SRLC16E
D
X
D
DS312-2 (v3.4) November 9, 2006
DS312-2_43_021305
Q[Am-1]
Q[Am]
Q
Q15
Q
Product Specification
Outputs
Q[15]
Q[15]
Q15
Table
20.
R