XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 15

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Table 6: Single-Ended IOSTANDARD Bank Compatibility
DS312-2 (v3.4) November 9, 2006
Product Specification
OCLK1
OCLK2
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
PCI66_3
PCIX
HSTL_I_18
IOSTANDARD
Single-Ended
PAD
D1
D2
From
Fabric
OCLK1
OCLK2
d
D1
D2
d+1
R
d
d+2
Figure 10: Output DDR
d+1
d+3
Output
Input/
1.2V
d+2
-
-
-
-
-
-
-
-
d+4
d+3
d+5
D
D
d+4
Output
Input/
Input
1.5V
V
Q
d+6
Q
CCO
-
-
-
-
-
-
-
d+5
d+7
Supply/Compatibility
d+6
Output
Output
d+8
DS312-2_23_030105
Input/
Input/
Input
Input
1.8V
d+7
-
-
-
-
-
PAD
d+9
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d+10
d+8
Output
Input/
Input
Input
Input
Input
2.5V
-
-
-
-
SelectIO Signal Standards
The Spartan-3E I/Os feature inputs and outputs that sup-
port a wide range of I/O signaling standards
Table
differential pairs to support any of the differential signaling
standards
To define the I/O signaling standard in a design, set the
IOSTANDARD attribute to the appropriate setting. Xilinx
provides a variety of different methods for applying the
IOSTANDARD for maximum flexibility. For a full description
of different methods of applying attributes to control
IOSTANDARD, refer to
straints” in the Xilinx Software Manuals and Help.
Spartan-3E FPGAs provide additional input flexibility by
allowing I/O standards to be mixed in different banks. For a
particular V
IOSTANDARDs that can be combined and if the IOSTAN-
DARD is supported as an input only or can be used for both
inputs and outputs.
7). The majority of the I/Os also can be used to form
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input
Input
Input
Input
Input
3.3V
(Table
CCO
voltage,
7).
“Entry Strategies for Xilinx Con-
Table 6
N/R
N/R
V
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
REF
Input Requirements
(1)
(1)
and
Functional Description
Table 7
Voltage (V
Termination
Board
list all of the
(Table 6
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
TT
and
)
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