XC3S100E-4CP132GI XILINX [Xilinx, Inc], XC3S100E-4CP132GI Datasheet - Page 88

• Manufacturer Part Number: XC3S100E-4CP132GI
• Description: Spartan-3E FPGA Family: Complete Data Sheet
• Manufacturer: XILINX [Xilinx, Inc]

Functional Description
Table 58: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
88
HDC
LDC2
A[23:0]
D[7:0]
CSO_B
BUSY
CCLK
D
Pin Name
FPGA Direction
Output
Output
Output
Output
Output
Output
Input
PROM Write Enable
PROM Byte Mode
Address
Data Input
Chip Select Output. Active Low.
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long or
has multiple connections, terminate
this output to maintain signal
integrity. See
Considerations.
Description
CCLK Design
www.xilinx.com
Connect to PROM write-enable
input (WE#). FPGA drives this
signal High throughout
configuration.
This signal is not used for x8
PROMs. For PROMs with a x8/x16
data width control, connect to
PROM byte-mode input (BYTE#).
See
Flash
signal Low throughout
configuration.
Connect to PROM address inputs.
High-order address lines may not
be available in all packages and
not all may be required. Number of
address lines required depends
on the size of the attached Flash
PROM. FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
FPGA receives byte-wide data on
these pins in response the
address presented on A[23:0].
Data captured by FPGA
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. If HSWAP = 1 in a
multi-FPGA daisy-chain
application, connect this signal to
a 4.7 kΩ pull-up resistor to
VCCO_2. Actively drives Low
when selecting a downstream
device in the chain.
Not used during configuration but
actively drives.
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration, drives
the CCLK inputs of all other
FPGAs in the daisy-chain.
Precautions Using x8/x16
During Configuration
PROMs. FPGA drives this
DS312-2 (v3.4) November 9, 2006
User I/O
User I/O. Drive this pin
High after configuration to
use a x8/x16 PROM in x16
mode.
User I/O
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
After Configuration
Product Specification
R