m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 97

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

register (PG), program counter (PC), and processor status register (PS) which were pushed onto the stack
area just before the INTACK sequence are automatically pulled. After this, the control returns to the original
routine. And then, the suspended processing, which was in progress before acceptance of the interrupt
request, is resumed.
be pulled in the same data length and register length as those in pushing, using the PUL instruction, etc.
that of the interrupt which is in progress, can be accepted by clearing the interrupt disable flag (I) to “0” in
an interrupt routine. In this way, multiple interrupts are processed.
RTI instruction is executed, the interrupt priority level of the routine which was in progress just before
acceptance of an interrupt request is pulled into the IPL. Therefore, if the following relationship is satisfied
when interrupt priority level detection is performed next, the retained interrupt request will be accepted.
Note: When any of the following interrupt requests is generated while an interrupt routine is in progress, this
INTERRUPTS
6.8 Return from interrupt routine, 6.9 Multiple interrupts
6.8 Return from interrupt routine
When the RTI instruction is executed at the end of the interrupt routine, the contents of the program bank
Before the RTI instruction is executed, registers which were pushed by software in the interrupt routine must
6.9 Multiple interrupts
Just after a branch is made to an interrupt routine, the following occur:
Accordingly, as long as the IPL remains unchanged, an interrupt request, whose priority level is higher than
Figure 6.9.1 shows the processing for multiple interrupts.
An interrupt request which has not been accepted because its priority level is lower is retained. When the
6-16
Retained interrupt request’s priority level > Processor interrupt priority level (IPL)
•Interrupt disable flag (I) = “1” (Interrupts are disabled.)
•Interrupt request bit of accepted interrupt = “0”
•Processor interrupt priority level (IPL) = Interrupt priority level of accepted interrupt
interrupt request is accepted at once: zero division, watchdog timer, and address matching detection.
7905 Group User’s Manual Rev.1.0