m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 306

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Fig. 11.4.12 Connection example
11.4.6 Receive operation
When the receive enable bit is set to “1,” the UARTi enters the receive-enabled state. Then, reception will
start when ST (’s falling edge) is detected and a transfer clock is generated.
If the RTS function selected, when connecting the RTS
timing of transmission and that of reception can be matched. If the RTS function selected, the RTS
output level becomes as described below.
When the receive enable bit = “0,” if one of the following is performed, the RTS
“L” and informs of the transmitter side that reception has become enabled:
• The receive enable bit is set to “1.”
• The low-order byte of the UARTi receive buffer register is read out.
When the receive enable bit = “1,” if the low-order byte of the UARTi receive buffer register is read out,
the RTS
Accordingly, when performing reception continuously, an overrun occurrence can be avoided because the
RTS output level does not become “L” until the receive data is read out.
When reception has started, the RTS
Figure 11.4.12 shows a connection example.
The receive operation is described below.
The receive complete flag is cleared to “0” when the low-order byte of the UARTi receive buffer register
has been read out. Figure 11.4.13 shows an example of receive timing when the transfer data length = 8
bits.
synchronously with the transfer clock’s rising edge.
several times according to the selected data format, the UARTi receive register’s contents are transferred
to the UARTi receive buffer register.
interrupt is selected (UARTi receive interrupt mode select bit = “0”), a UARTi receive interrupt request
occurs and its interrupt request bit is set to “1.”
When one set of data has been prepared, in other words, when the shift operation has been performed
The signal input to the RxD
The contents of the UARTi receive register are shifted, bit by bit, to the right.
Steps
Simultaneously with step
i
pin’s output level becomes “L.”
and
are repeated at each rising edge of the transfer clock.
Transmitter side
, the receive complete flag is set to “1.” Additionally, when the receive
i
pin is taken into the most significant bit of the UARTi receive register,
CTS
RxD
TxD
i
i
i
7905 Group User’s Manual Rev.1.0
i
pin’s output level becomes “H.”
11.4 Clock asynchronous serial I/O (UART) mode
i
pin to the CTS
TxD
RxD
RTS
Receiver side
i
i
i
i
pin of the transmitter side, the
i
pin’s output level becomes
SERIAL I/O
i
11-51
pin’s