m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 227
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m37905
Manufacturer Part Number
m37905
Description
Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M37905.pdf
(565 pages)
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THREE-PHASE WAVEFORM MODE
10.2 Block description
Fig. 10.2.7 Structure of three-phase output data register 1 (three-phase waveform mode)
10-10
10.2.4 Three-phase output data register 1
Figure 10.2.7 shows the structure of the three-phase output data register 1 (the three-phase waveform
mode).
Three-phase output data register 1 (Address A9
X: It may be either “0” or “1.”
Notes 1: Valid when the W-phase output fix bit (bit 0 at address A8
7, 6
Bit
0
1
2
3
4
5
2: Valid when the V-phase output fix bit (bit 1 at address A8
3: Valid when the U-phase output fix bit (bit 2 at address A8
fixed value.
fixed value.
fixed value.
W-phase fixed output’s polarity
set bit
V-phase fixed output’s polarity
set bit
U-phase fixed output’s polarity
set bit
Invalid in the three-phase waveform mode.
V-phase output polarity set buffer
(in three-phase mode 0)
Interrupt request interval set bit
(in three-phase mode 1)
U-phase output polarity set buffer
(in three-phase mode 0)
Interrupt validity output select bit
(in three-phase mode 1)
Invalid in the three-phase waveform mode.
Bit name
(Note 1)
(Note 2)
(Note 3)
7905 Group User’s Manual Rev.1.0
0 : “H” output fixed
1 : “L” output fixed
0 : “H” output fixed
1 : “L” output fixed
0 : “H” output fixed
1 : “L” output fixed
0 : “H” output
1 : “L” output
0 : Every second time
1 : Every forth time
0 : “H” output
1 : “L” output
0 : An interrupt request occurs at each even-number-
1 : An interrupt request occurs at each odd-number-
ed underflow of timer A3
ed underflow of timer A3
16
)
16
16
16
) = “1.” Be sure not to change the value during output of a
) = “1.” Be sure not to change the value during output of a
) = “1.” Be sure not to change the value during output of a
Function
b7 b6 b5 b4 b3 b2 b1 b0
X X
At reset
X
0
0
0
0
0
0
0
R/W
RW
RW
RW
RW
RW
RW
RW
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