m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 278

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Table 11.3.3 Relationship between transfer data format and writing/reading to and from UARTi transmit/
11.3.2 Transfer data format
LSB first or MSB first can be selected as the transfer data format. Table 11.3.3 lists the relationship
between the transfer data format and writing/reading to and from the UARTi transmit/receive buffer register.
The transfer format select bit (bit 7 at addresses 34
this bit is cleared to “0,” the set data is written to the UARTi transmit buffer register as the transmit data,
as it is. Similarly, the data in the UARTi receive buffer register is read out as the receive data, as it is.
(See the upper row in Table 11.3.3.) When this bit is set to “1,” each bit’s position of set data is reversed,
and the resultant data will be written to the UARTi transmit buffer register as the transmit data. Similarly,
each bit’s position of data in the UARTi receive buffer register is reversed, and the resultant data will be
read out as the receive data. (See the lower row in Table 11.3.3.)
Note that only the method of writing/reading to and from the UARTi transmit/receive buffer register is
affected by selection of the transfer data format, and that the transmit/receive operation is unaffected by
it.
Transfer format
select bit
0
1
receive buffer register
(Least Significant Bit)
Transfer data format
(Most Significant Bit)
MSB
LSB
first
first
7905 Group User’s Manual Rev.1.0
Writing to UARTi transmit buffer
Data bus
Data bus
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
16
register
11.3 Clock synchronous serial I/O mode
, 3C
UARTi transmit
buffer register
UARTi transmit
buffer register
16
D
D
D
D
D
D
D
D
, B4
7
6
5
4
3
2
1
0
D
D
D
D
D
D
D
D
16
7
6
5
4
3
2
1
0
) selects the transfer data format. When
Data bus
Data bus
Reading from UARTi receive
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
buffer register
SERIAL I/O
UARTi receive
buffer register
UARTi receive
buffer register
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
D
D
D
D
D
D
D
D
7
6
5
4
3
2
1
0
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