m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 32

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

(6) Bit 5: Data length flag (m)
(7) Bit 6: Overflow flag (V)
(8) Bit 7: Negative flag (N)
(9) Bits 10 to 8: Processor interrupt priority level (IPL)
as a 16-bit unit when this flag is “0,” and as an 8-bit unit when it is “1” (Note).
CLP instruction to clear it to “0.”
The overflow flag is set to “1” when the result of addition or subtraction exceeds the range between
+32767 (when 16-bit length operation), or the range between –128 and +127 (when 8-bit length
operation).
the length of the register which will store that result. This flag is invalid in the decimal mode. Be sure
to use the SEP instruction to set this flag to “1,” and be sure to use the CLV or CLP instruction to
clear it to “0.”
significant bit of the result is “1.”) It is cleared to “0” in all other cases. This flag is invalid in the
decimal mode. Be sure to use the SEP instruction to set this flag to “1,” and be sure to use the CLP
instruction to clear it to “0.”
the interrupt priority level of a requested interrupt, which has been set in the corresponding interrupt
control register, is higher than IPL, that interrupt becomes enabled. When an interrupt request is
accepted, IPL is stored in the stack area, and IPL is replaced by the interrupt priority level of the
accepted interrupt request.
new IPL into the stack area and updating PS with the PUL or PLP instruction.
This flag determines whether to use data as a 16-bit unit or as an 8-bit unit. Each data is treated
Be sure to use the SEM or SEP instruction to set this flag to “1,” and be sure to use the CLM or
This flag is cleared to “0” at reset.
Note: When transferring data between registers which are different in bit length, this data is transferred
This flag is used when addition or subtraction is performed with a word regarded as signed binary.
–2147483648 and [phone] (when 32-bit length operation), the range between –32768 and
The overflow flag is also set to “1” when the operation result of the DIV or DIVS instruction exceeds
The contents of this flag is undefined at reset.
This flag is set to “1” when the result of arithmetic operation or data transfer is negative. (The most
The contents of this flag is undefined at reset.
These 3 bits can determine the processor interrupt priority level to one of levels 0 through 7. When
There are no instruction to directly set or clear the bits of IPL. IPL can be changed by storing the
The contents of IPL is cleared to “000
with the length of the transfer destination register, except for the case where the TXA, TYA,
TXB, TYB, and TXS instructions used. Refer to “7900 series software manual” for detail.
CENTRAL PROCESSING UNIT (CPU)
7905 Group User’s Manual Rev.1.0
2
” at reset.
2.1 Central processing unit (CPU)
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