m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 374

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Before executing the STP instruction, be sure to enable an interrupt which is to be used for the stop mode
termination.
Also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination, is
higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is executed.
After oscillation starts ( ), there is a possibility that each interrupt request occurs until the supply of
after the watchdog timer’s MSB becomes “0.” (When the level sense of an INT
no interrupt request is retained. Therefore, if pin INT
becomes “0,” no interrupt request is accepted.) For an interrupt which has no need to be accepted, be sure
to set its interrupt priority level to “0” (Interrupt disabled) before executing the STP instruction.
15.3.2 Terminate operation at interrupt request occurrence (when not using watchdog timer)
At the stop mode termination, an instruction is executed without use of the watchdog timer. (See Figure
15.3.1.)
Before executing the STP instruction, be sure to set as follows:
Note: Simultaneously, the oscillation driver circuit between pins X
BIU
Enable an interrupt which is to be used for the stop mode termination.
The external clock input select bit (bit 1 at address 62
The system clock select bit (bit 5 at address BC
When an interrupt request occurs, clock input from pin X
Supply of
The interrupt request which occurred in
Also, make sure that the interrupt priority level of an interrupt, which is to be used for the termination,
is higher than the processor interrupt priority level (IPL) of a routine where the STP instruction is
executed.
1
starts ( ). The interrupt requests which occurred during this period are accepted in order of priority
, f
1
at pin X
to f
4096
CPU
, Wf
OUT
,
is kept “H.” (Refer to section “16.3 Stop of oscillation circuit.”)
32
BIU
, Wf
starts after the time listed in Table 15.3.2 has elapsed.
512
starts.
7905 Group User’s Manual Rev.1.0
is accepted.
i
16
is at the invalid level when the watchdog timer’s MSB
) = “0” (Note)
Table 15.3.2 Time after stop mode is terminated
select bits at STP termination
Watchdog timer clock source
(bits 7, 6 at address 61
STOP AND WAIT MODES
16
) = “1” (Note)
IN
starts. Simultaneously, supply of clocks f
00
01
10
11
IN
until supply of
and X
OUT
16
i
)
stops, and the output level
interrupt is used, however,
Time until supply of
15.3 Stop mode
CPU
CPU
fX
fX
fX
fX
,
IN
IN
IN
IN
and
BIU
19 cycles
11 cycles
67 cycles
35 cycles
starts
BIU
starts
15-9
CPU
sys
,
,