m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 373

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

operation becomes inactive. This state is called “stop mode.” (See Table 15.1.1)
if Vcc (the power source voltage)
peripheral devices which use any of clocks f
can be saved.
termination if all of the following conditions are satisfied. (Refer to section “15.3.2 Terminate operation at
interrupt request occurrence (when not using watchdog timer).”):
stabilizing time has been measured by using the watchdog timer if any of the following conditions is satisfied.
(Refer to section “15.3.1 Terminate operation at interrupt request occurrence (when using watchdog
timer).”):
STOP AND WAIT MODES
15.3 Stop mode
15.3 Stop mode
When the STP instruction has been executed, each of the oscillation and the PLL frequency multiplier’s
In the stop mode, even when oscillation becomes inactive, the contents of the internal RAM can be retained
The stop mode is terminated owing to an interrupt request occurrence or hardware reset.
When terminated owing to an interrupt request occurrence, an instruction can be executed immediately after
• An stable clock is input from the external. (The external clock input select bit (bit 1 at address 62
• The PLL frequency multiplier is not used. (The system clock select bit (bit 5 at address BC
When terminated owing to an interrupt request occurrence, an instruction will be executed after the oscillation
• An oscillator is used. (The external clock input select bit (bit 1 at address 62
• The PLL frequency multiplier is used. (The system clock select bit (bit 5 at address BC
Table 15.3.1 Interrupts which can be used to terminate stop mode
15-8
Notes 1: When multiple interrupts are enabled, the stop mode is terminated owing to the interrupt request which occurs first.
INT
Timer Ai interrupt (i = 0 to 9)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0 to 2)
UARTi receive interrupt (i = 0 to 2)
15.3.1 Terminate operation at interrupt request occurrence (when using watchdog timer)
At the stop mode termination, execution of an instruction is started after a certain time has been measured
by using the watchdog timer. (See Figure 15.3.1.)
For the watchdog timer, refer to “CHAPTER 14. WATCHDOG TIMER.”
Table 15.3.1 lists the interrupts which can be used to terminate the stop mode.
When an interrupt request occurs, an oscillator starts its operation. Also, when the PLL circuit operation
When the most significant bit (MSB) of the watchdog timer becomes “0,” each supply of
By start of oscillation in
The interrupt request which occurred in
enable bit (bit 1 at address BC
with this, each supply of clocks f
frequency select bit (bit 0 at address 61
which is selected by the watchdog timer clock source select bits at STP termination (bits 7, 6 at address
61
(At this time, no watchdog timer interrupt request occurs.) Also, the count source of the watchdog timer
returns to the count source selected by the watchdog timer frequency select bits (in order words, Wf
or Wf
i
interrupt (i = 0 to 7)
16
2: For interrupts, refer to “CHAPTER 6. INTERRUPTS” and each peripheral device’s chapter.
). This counting is started from a value of “FFF
512
).
Interrupt
, the watchdog timer starts its operation. Regardless of the watchdog timer
16
) = “1,” the PLL frequency multiplier starts its operation. Simultaneously
sys
V
7905 Group User’s Manual Rev.1.0
RAM
,
1
In event counter mode
When an external clock is selected.
, f
(RAM hold voltage). Furthermore, since the CPU and internal
1
to f
1
16
to f
), the watchdog timer counts a count source (fX
is accepted.
4096
4096
, Wf
Usage condition for interrupt request occurrence
, Wf
32
, Wf
16
32
.”
, Wf
512
512
stop their operations, the power consumption
starts.
16
) = “0.”)
16
) = “1.”)
CPU
16
,
) = “0.”)
16
16
BIU
to fX
) = “1.”)
starts.
128
),
32