m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 83

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

in the interrupt vector table (addresses FFB4
the corresponding interrupt vector address in the interrupt vector table.
When an interrupt request is accepted, the following
registers’ contents just before acceptance of an
interrupt request are automatically pushed onto the
stack area in ascending sequence from
For other registers of which contents are necessary,
be sure to push and pop them by software.
Figure 6.1.2 shows the state of the stack area just
before entering an interrupt routine.
Execute the RTI instruction at the end of this interrupt
routine in order to return to the routine that the
microcomputer was executing just before the interrupt
request was accepted. By executing the RTI instruction,
the register contents pushed onto the stack area are
pulled in descending sequence from
the suspended processing is resumed from where it
left off.
INTERRUPTS
6.1 Overview
6.1 Overview
The M37905 provides 32 (including the reset) interrupt sources to generate interrupt requests.
Figure 6.1.1 shows the interrupt processing sequence.
When an interrupt request is accepted, a branch is made to the start address of the interrupt routine set
Fig. 6.1.1 Interrupt processing sequence
6-2
Interrupt request is accepted.
Program bank register (PG)
Program counter (PC
Processor status register (PS
Processing is resumed.
L
Processing is suspended.
, PC
Routine in progress
H
)
L
, PS
7905 Group User’s Manual Rev.1.0
to
H
to
)
. Then,
16
to FFFF
.
Fig. 6.1.2 State of stack area just before entering
16
). Set the start address of each interrupt routine to
[S] – 5
[S] – 4
[S] – 3
[S] – 2
[S] – 1
Address
[S]
[S] is an initial address that the stack pointer (S) indicates
when an interrupt request is accepted. The S’s contents
become “[S] – 5” after all of the above registers are pushed.
Processor status register’s high-order byte (PS
interrupt routine
Processor status register’s low-order byte (PS
Program counter’s high-order byte (PC
Program counter’s low-order byte (PC
Interrupt routine
RTI instruction
Program bank register (PG)
Stack area
Interrupt processing
L
H
)
)
L
H
)
)