m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 317

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m37905

Manufacturer Part Number
m37905
Description
Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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A-D CONVERTER
Fig. 12.2.3 Structure of A-D control register 1
12-6
12.2 Block description
Notes 1: These bits are invalid in the one-shot and repeat modes. (They may be either “0” or “1.”)
A-D control register 1 (Address
Bit
0
1
2
3
4
5
6
7
2: When using pin AN
3: Be sure to select frequently-used analog input pins in the repeat sweep mode 1.
4: Fix this bit to “0” in the one-shot mode, repeat mode, and single sweep mode.
5: When this bit is cleared from “1” to “0,” be sure to start the A-D conversion after an interval of 1 µs or more has elapsed.
6: Writing to each bit of the A-D control register 1 must be performed while the A-D converter halts, regardless of the A-D
operation mode.
A-D sweep pin select bits
(Valid in the single sweep mode,
repeat sweep mode 0 and
A-D operation mode select bit 1
(Used in the repeat sweep mode 0
and repeat sweep mode 1.)(Note 4)
Resolution select bit
A-D conversion frequency (
Fix this bit to “0.”
V
The value is “0” at reading.
repeat sweep mode 1.)
REF
connection select bit (Note 5)
Bit name
7
, be sure that the D-A
AD
) select bit 1
1F
(Note 1)
16
7905 Group User’s Manual Rev.1.0
)
0
output enable bit (bit 0 at address 96
0 : Pin V
1 : Pin V
0 : Repeat sweep mode 0
1 : Repeat sweep mode 1
0 : 8-bit resolution mode
1 : 10-bit resolution mode
See Table 12.2.1.
b1 b0
b1 b0
Single sweep mode/Repeat sweep mode 0
0 0 : Pins AN
0 1 : Pins AN
1 0 : Pins AN
1 1 : Pins AN
Repeat sweep mode 1
0 0 : Pin AN
0 1 : Pins AN
1 0 : Pins AN
1 1 : Pins AN
REF
REF
is connected.
is disconnected.
0
0
0
0
0
0
0
0
(1 pin)
and AN
to AN
to AN
to AN
and AN
to AN
to AN
3
5
7
2
3
Function
(4 pins)
(6 pins)
(8 pins) (Note 2)
(3 pins)
(4 pins)
1
1
(2 pins)
(2 pins)
(Note 3)
16
) = “0” (output disabled).
b7 b6 b5 b4 b3 b2 b1 b0
0
At reset
1
1
0
0
0
0
0
0
R/W
RW
RW
RW
RW
RW
RW
RW

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