m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 40

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Fig. 2.4.2 SFR area’s memory map (1)
Address
1C
1D
2C
2D
3C
3D
1A
1B
1E
2A
2B
2E
3A
3B
3E
10
11
12
13
14
15
16
17
18
19
1F
20
21
22
23
24
25
26
27
28
29
2F
30
31
32
33
34
35
36
37
38
39
3F
C
D
A
B
E
0
1
2
3
4
5
6
7
8
9
F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Notes 1: Do not read from and write to this register.
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 transmit/receive mode register
UART0 transmit/receive mode register
UART0 baud rate register (BRG0)
UART1 baud rate register (BRG1)
2: Do not write to this register.
3: When these registers are accessed, set the address compare register access enable bit (bit 2 at address 67
4: This register is assigned only to the flash memory version. (Refer to “CHAPTER 19. FLASH MEMORY VERSION.”)
UART0 transmit buffer register
UART1 transmit buffer register
UART1 receive buffer register
UART0 receive buffer register
(Refer to “CHAPTER 17. DEBUG FUNCTION.”)
Nothing is assigned here in the mask ROM version.
Port P1 direction register
Port P2 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Port P8 direction register
A-D control register 0
A-D control register 1
Port P1 register
Port P2 register
Port P4 register
Port P5 register
Port P6 register
Port P7 register
Port P8 register
A-D register 0
A-D register 1
A-D register 2
A-D register 3
A-D register 4
A-D register 5
A-D register 6
A-D register 7
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 1)
(Note 1)
CENTRAL PROCESSING UNIT (CPU)
Address
7905 Group User’s Manual Rev.1.0
4A
4B
4C
4D
4E
5A
5B
5C
5D
5E
6A
6B
6C
6D
6E
7A
7B
7C
7D
7E
4F
5F
6F
7F
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Watchdog timer frequency select register
UART0 transmit interrupt control register
UART1 transmit interrupt control register
A-D conversion interrupt control register
UART0 receive interrupt control register
UART1 receive interrupt control register
Address compare register 0 (Note 3)
Address compare register 1 (Note 3)
Timer A clock division select register
Particular function select register 0
Particular function select register 1
Particular function select register 2
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
INT
INT
INT
INT
Processor mode register 0
Processor mode register 1
Watchdog timer register
Debug control register 0
Debug control register 1
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
3
4
0
1
2
One-shot start flag 0
One-shot start flag 1
interrupt control register
interrupt control register
interrupt control register
interrupt control register
interrupt control register
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
Count start flag 0
Count start flag 1
Up-down flag 0
(Note 2)
Address
8C
8D
9C
9D
8A
8B
8E
8F
9A
9B
9E
9F
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
2.4 Memory assignment
16
Flash memory control register (Note 4)
) to “1.”
External interrupt input read register
D-A control register
D-A register 0
D-A register 1
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
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