SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 82
SDA9410-B13
Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
1.SDA9410-B13.pdf
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SDA9410
Figure 38
The polarity of the VOUT signal is programmable by the I²C Bus parameter VOUTPOL.
The VOUT signal has a delay of two CLKOUT clocks to the HOUT signal or in case of
interlaced a delay of a half line plus two CLKOUT clocks.
The INTERLACED signal can be used for AC-coupled deflections. Depending on the I²C
Bus parameter INTMODE the value of this signal will be generated. The Table 69 shows
the definition of this signal (compare "Operation mode generator" on page 83).
Table 69
Table 70
82
INTMODE
I²C Bus
parameter
VOUTFR
1: free run
0: locked
mode
RMODE
1: progressive
0: interlaced
INTMODE
VOUT
VOUT
VIN
VOUT generation depending on I²C Bus parameter RMODE
Output write I²C Bus parameter INTMODE
Output write I²C Bus parameter INTMODE
output field phase
0
INTMODE(0)
Sub address
4Ah
48h
49h
RMODE=1
RMODE=0
output field phase
1
INTMODE(1)
VOUT generator mode select
line-scanning pattern mode
Free programmable INTERLACED signal for AC-coupled
deflection stages
Description
Output sync controller (OSCM/S)
output field phase
2/0
INTMODE(2)
Preliminary Data Sheet
output field phase
3/1
INTMODE(3)
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