SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 133
SDA9410-B13
Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
1.SDA9410-B13.pdf
(179 pages)
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SDA9410
133
Sub address 10
Bit
D7...D0
Sub address 11
Bit
D7...D2
D1
D0
Sub address 12
Bit
D7
D6...D2
D1...D0
Name
ALPFIPM
Name
VINDELM
VINPOLM VINM polarity:
HINPOLM HINM polarity:
Name
x
NALIPM
CHRFOR
M
Function
Number of active lines per field in the input data stream master:
Active lines = ALPFIPM * 2 [ALPFIPM=144]
Function
VINM input delay:
Delay(VINM to internal V-sync) = (128 * VINDELM + 1)*Tclkm
[VINDELM = 0]
1: low active
0: high active
1: low active
0: high active
Function
x
Number of not active lines per field in the input data stream
master:
Not active lines = NALIPM+3 [NALIPM= 20]
Chrominance Format Master Channel:
11: not defined
10: reserved
01: 4:2:0
00: 4:1:1
Preliminary Data Sheet
Micronas
I²C Bus
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