SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 128
SDA9410-B13
Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
1.SDA9410-B13.pdf
(179 pages)
- Current page: 128 of 179
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SDA9410
128
Sub address 03
Bit
D4...D2
D1...D0
Sub address 04
Bit
D7...D5
D4
D3...D0
Name
RIBORDM Amount of right border pixels by horizontal compression
CHFILM
Name
DELM
FORCOLM
YBORDERM
Function
master: 4*RIBORDM [RIBORDM=0]
Chrominance Filter Master channel on/off
11: vertical and horizontal filter on (only valid for
DEZHM=DEZVM=0)
10: horizontal filter on (only valid for DEZHM=0)
01: vertical filter on (only valid for DEZVM=0)
00: off
Function
Adjustable delay between luminance and chrominance data
master channel:
111:+4
110:+3
101:+2
100:+1
011: 0
010: -1
001: -2
000: -3
Force colour master channel
1: on
0: off
Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0
0 0 0 = 00010000 = 16), YBORDERM defines the 4 MSB’s of a
8 bit value
Preliminary Data Sheet
Micronas
I²C Bus
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