SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 14

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
3
Figure 1
The SDA 9410 contains the blocks, which will be briefly described below:
ISCM/S - Flexible input sync controller
IFCM/S - Input format conversion, Adjustable delay
VHCOMM/S - Vertical and horizontal compression, horizontal expansion, panorama mode (only M)
TSNR - Temporal and spatial noise reduction, noise measurement
LBD - Letter box detection
ME - Motion estimation, Film mode and phase detection
MC - Memory controller
OSCM/S - Flexible output sync controller
OFC - Output format conversion, 4:4:4, 8:8:8 interpolation, Adjustable delay
SRCM/S - Scan rate conversion, vertical expansion
MUX - Combination of the two output channels
DLTI/DCTI/Peaking - Luminance and chrominance transition improvement, luminance peaking
I
PLLM/S/D - PLL for frequency doubling
LM - Line memory core, VM - Vector memory core
ED - eDRAM core
14
2
C - I²C bus interface
SYNCENM
SYNCENS
UVINM
UVINS
CLKM
YINM
YINS
HINM
VINM
CLKS
HINS
VINS
doubling
doubling
PLLM
clock
clock
PLLS
conversion
conversion
Input sync controller Master
Input sync controller Slave
Block diagram
format
format
Input
IFCM
Input
IFCS
Block diagram
ISCS
ISCM
compression/
compression/
Line memory
Line memory
Vertical and
Vertical and
horizontal
expansion
horizontal
expansion
VHCOMM
VHCOMS
LM
LM
Temporal,
reduction
TEST
spatial
TSNR
noise
detection
Letter
LBD
box
RESET
Controller
controller
Memory
eDRAM
Voltage
control
Buffer
Test-
MC
ED
+
+
+
memory
estimation
memory
Line
Vector
motion
LM
VM
ME
conversion
expansion
Scan rate
Vertical
Master
SRCM
SRCS
X2
M
U
X
doubling
clock
PLLD
Peaking
DLTI
DCTI
X1/CLKD
Output sync
controller
OSCM/S
Master
Preliminary Data Sheet
Framing
Delay
4:4:4
8:8:8
OFC
SDA
Block diagram
I²C
SCL
DAC
DAC
DAC
Micronas
YO
UO
CLKOUT
INTERLACED
BLANK
VO
HOUT
VOUT