SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 77

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
5.7
Table 67
The output sync controller generates horizontal and vertical synchronization signals for
the scan rate converted output signal. The figure below shows the block diagram of the
OSCM/S and the existing I²C Bus parameters.
Figure 34
Furthermore the output sync controller derives framing signals from the generated
HOUT and VOUT for the output data processing. The framing signals depend on
different I²C Bus parameters. The whole output picture is a combination of three
channels:
77
Signals
HOUT
VOUT
BLANK
INTERLACED
GMOTION,
MOVMO,
MOVTYP
MOVPH,
Output sync controller (OSCM/S)
STOPMOM, STOPMOS,
Output signals
Block diagram of OSCM/S
HIN
VIN
Pin number
4
5
7
6
ADOPMOM
OPERATION
generator
mode
HORWIDTHM, HORWIDTHS, HOUTDEL
NAPOPD, BLANLEN, PPLOP, RMODE,
BLANDEL, HORPOSM, HORPOSS,
HOUTPOL, HOUTFR, APPLOPD,
Description
horizontal synchronization signal (polarity programmable, I²C Bus
parameter 4Ah HOUTPOL, default: high active)
vertical synchronization signal (polarity programmable, I²C Bus
parameter 4Ah VOUTPOL, default: high active)
free programmable horizontal blanking signal (polarity
programmable, I²C Bus parameter 49h BLANKPOL, default: high
active)
interlaced signal (can be used for AC coupled deflection circuits)
VERPOSS, VERWIDTHM,
VERWIDTHS, INTMODE
VOUTPOL, VOUTFR,
NALOPD, ALPFOPD,
LPFOP, VERPOSM,
generator
generator
HOUT
VOUT
Output sync controller (OSCM/S)
Preliminary Data Sheet
BLANK
HOUT
VOUT
INTERLACED
Micronas