SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 145
SDA9410-B13
Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
1.SDA9410-B13.pdf
(179 pages)
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SDA9410
145
Sub address 34
Bit
D7...D1
D0
Sub address 35
Bit
D7...D0
Sub address 36
Bit
D7...D0
Sub address 37
Bit
D7
D6...D0
Name
NALIPS
CHRFORS
Name
HOUTDEL Horizontal delay of HOUT and VOUT signal in clocks of CLKD:
Name
NALOPD
Name
ALPFOPD Number of active lines per output frame:
Function
Number of not active lines per field in the input data stream
slave:
Not active lines = NALIPS+PD [NALIPS= 20]
Enables 16x9 format adjustment for PIP display
Chrominance format slave channel:
1: 4:2:0
0: 4:1:1
Function
Delay = 4*HOUTDEL [HOUTDEL = 0]
Function
Number of not active lines per output frame in the output data
stream:
Not active lines = 2*(NALOPD+1) [NALOPD = 22]
Function
x
Active lines = 8 * ALPFOPD [ALPFOPD= 72]
Preliminary Data Sheet
Micronas
I²C Bus
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