SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 57

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
5.6.2
The following Table 42 and Table 43 summarize all possible combinations of memory
data configurations for the master and slave channel and the corresponding
applications. The main configurations are no. 1 for motion compensated up conversion
and PIP insertion, no. 5 for joint line free Split Screen display and no. 9 for high quality
Multi Picture including one live channel.
Table 44 shows the possible picture sizes. The data formats can be always 4:2:0 or
4:1:1. In SSC and MUP mode the picture sizes are influenced by the I²C Bus parameters
MEMWRM and MEMWRS.
Table 42
57
Config.
10
11
12
1
2
3
4
5
6
7
8
9
Configuration controlling
MEMOP
Programmable data configurations
00
00
00
00
01
01
01
01
10
10
10
10
ORGMEMM
1
1
0
0
1
1
0
0
1
1
0
0
ORGMEMS
Application modes and memory concept
1
0
1
0
1
0
1
0
1
0
1
0
Fields
Master Channel
Y
2
2
1
1
2
2
1
1
2
2
1
1
Preliminary Data Sheet
C
2
2
1
1
2
2
1
1
2
2
1
1
Fields
Slave Channel
not available
Y
3
3
2
1
2
1
2
1
2
1
2
1
Micronas
C
3
3
2
1
2
1
2
1
2
1
2
1