SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 34
SDA9410-B13
Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
1.SDA9410-B13.pdf
(179 pages)
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SDA9410
Table 11
Table 12
The vertical compression block can be switched off by setting DEZVM/DEZVS equal “0”
and INTVM/INTVS=0. In this case it is possible to switch on a low pass filter for the
chrominance data path by the I²C Bus parameter CHFILM/CHFILS (I²C Bus parameter,
03h, 25h). If CHFILM/CHFILS is equal to “0” or “2” the vertical filter for the chrominance
is switched off. If CHFILM/CHFILS is equal to “1” or “3” the vertical filter for the
chrominance is switched on (Table 17 "Input write I²C Bus parameter CHFILM/
CHFILS" on page 38).
In addition a vertical peaking of the input signal is possible.
34
Vertical line size
2*ALPFM/S
(2*ALPFIPM/S=288)
288
216
192
145
144
96
73
72
36
18
10
Examples of vertical filter adjustment
Conversion table between dezV and DEZVM / DEZVS
dezV
16
8
4
2
1
INTVM/S
0
171
256
505
0
256
497
0
0
0
409
DEZVM / DEZVS
111
110
101
100
001
dezV/DEZVM/S
1/1
1/1
1/1
1/1
2/4
2/4
2/4
4/5
8/6
16/7
16/7
Input signal processing
Comment
largest size, bypass
recommended DEZVM/
DEZVS=0
Double window
PIP (1/3 picture)
smallest size
Preliminary Data Sheet
Micronas
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