SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 24

• Manufacturer Part Number: SDA9410-B13
• Description: Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
• Manufacturer: MICRONAS [Micronas]

SDA9410
Figure 8
Table 4
In case of non-standard signals the field order is indeterminate (e.g. AAA... , BBB... ,
AAABAAAB..., etc.). Therefore a special filtering algorithm is implemented, which can be
switched on by the I²C Bus parameter VCRMODEM/VCRMODES. It is recommended to
set the I²C Bus parameter VCRMODEM=1. In other case (VCRMODEM=0) an additional
24
VINM
VINM
Ffd
Ffd
CLKM
H1
H2
I²C Bus parameter
[Default value]
VINDELM
[0]
VINDELS
[0]
FIEINVM
[0]: Field A=0
FIEINVS
[0]: Field A=0
VCRMODEM
[1]: on
VCRMODES
[1]: on
Vd
Vd
1 : Field A=1
1 : Field A=1
0 : off
0 : off
Field detection and VINM delay
Input write I²C Bus parameter
Sub address
11h
33h
0Bh
2Dh
0Bh
2Dh
(VINDELM * 128 + 1) *
x
Tclkm
x
(VINDELM * 128 + 1) *
Description
Delay of the incoming V-Sync VINM (must be adjusted
depending on the delay of the HINM signal)
Delay of the incoming V-Sync VINS (must be adjusted
depending on the delay of the HINS signal)
Inversion of the internal field polarity master
Inversion of the internal field polarity slave
In case of non standard interlaced signals (VCR, Play-
Stations) a filtering of the internal field signal has to be done
(should also be used for normal TV signals)
In case of non standard interlaced signals (VCR, Play-
Stations) a filtering of the internal field signal has to be done
(should also be used for normal TV signals)
Tclkm
Input sync controller (ISCM/ISCS)
Field 1(A)
Preliminary Data Sheet
Field 2(B)
Micronas