SDA9410-B13 MICRONAS [Micronas], SDA9410-B13 Datasheet - Page 29

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SDA9410-B13

Manufacturer Part Number
SDA9410-B13
Description
Display Processor and Scan Rate Converter using Embedded DRAM Technology Units
Manufacturer
MICRONAS [Micronas]
Datasheet
SDA9410
Figure 10
The Figure 11 shows the input timing and the functionality of the NAPIPDLM/NAPIPDLS
and NAPIPPHM/NAPIPPHS I²C Bus parameter in case of CCIR 656 and 4:2:2 parallel
data input format for one example. The signals HINMint, YINMint and UVMint are the
internal available sampled input signals.
Figure 11
29
HINMint
UVINMint
HINM/VINM
YINMint
HINMen/VINMen
HINM
YINM
UVINM
YINMint
UVINMint
YINM
CCIR 656 interface
UVINMen
YINMen
4:2:2 interface
SYNCENM
YINM
UVINM
CLKM
CLKM
SYNCENM/SYNCENS signal
Input timing
x
x
x
x
y0
u0
(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm
=(0 * 4 + 3 + 7) * Tclkm = 10 Tclkm (e.g.)
(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm
=(0 * 4 + 2 + 7) * Tclkm = 9 Tclkm (e.g.)
y0
u0
v0
y1
xxx
xxx
xxx
v0
y1
y2
u2
y2
u2
y3
v2
Input format conversion (IFCM/IFCS)
y3
v2
u0
y0
u0
y0
u0
v0
y0
u0
y0
u0
v0
y1
y1
v0
Preliminary Data Sheet
u2
y1
v0
y1
v0
y2
u2
y2
u2
v2
y2
u2
y3
u2
y3
v2
y3
Micronas
v2
u4
v2
v2
y3
y4
u4
y4
u4
y4

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