S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 92

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

S1D15206 Series
6. FUNCTION DESCRIPTION
MPU Interface
Parallel/Serial Interface
The S1D15206 series can transfer data via 8-bit bidirectional data buses D0 to D7 or via serial data input D7 (SI). The 8-bit parallel data input
or serial data input, 8080/6800-series microprocessor, and reset status can select according to SR1 and SR2.
No data can be read from RAM and no status can be read during serial data input. Also, RD and WR are high or low, and D0 to D5 are open.
Data Bus Signals
The S1D15206 series identifies the data bus signal according to A0, RD, and WR (E, R/W) signals.
Serial Interface (SR1 is high and SR2 is low)
The serial interface consists of an 8-bit shift register and a 3-bit
counter. The serial data input and serial clock input are enabled
when CS1 is low and CS2 is high (in chip select status). When chip
is not selected, the shift register and counter are reset.
When serial data input is enabled by SR1 and SR2, D7 (SI) receives
serial data and D6 (SCL) receives serial clock. Serial data of D7, D6,
..., D0 is read at D7 in this sequence when serial clock goes high.
They are converted into 8-bit parallel data and processed on rising
4–8
SR1
Common
0
1
1
0
* When set for the 68 family interface, the SR1 and SR2 timing must match or SR1 must rise first.
A0
1
1
0
0
SR2
1
1
0
0
SR1
SR2
6800 processor
8080 microprocessor
bus (parallel)
6800 microprocessor
bus (parallel)
Serial input
Reset
WR (R/W)
1
0
1
0
Type
RESET
8080 processor
RD
0
1
0
1
WR
CS1
CS1
CS1
CS1
CS1
1
0
1
0
EPSON
Reads display data.
Writes display data.
Reads status.
Writes control data in internal register. (commands)
CS2
CS2
CS2
CS2
CS2
Table 1
Table 2
edge of every eighth serial clock signal.
The serial data input is determined to be the display data when A0
is high, and it is control data when A0 is low. A0 is read on rising
edge of every eighth clock signal.
Figure 1 shows a timing chart of serial interface signals. The serial
clock signal must be terminated correctly against termination reflec-
tion and ambient noise. Operation checkout on the actual machine
is recommended.
A0
A0
A0
A0
A0
The 68 family interface
RD
RD
0/1
RD
E
R/W
WR
WR
WR
0/1
Function
D0 to D7
D0 to D7
D6 (SCL) and D7 (SI)
— — — — — — —
Data (D0 to D7)
Rev.3.5