S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 35
S1D1
Manufacturer Part Number
S1D1
Description
LCD Controller-driver With Built-in Character ROM
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D1.pdf
(612 pages)
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S1D15200 Series
(7) Common Timing Generator Circuit
Generates common timing signals and FR frame signals
from the CL basic clock. The 1/16 or 1/32 duty (for
S1D15200) or 1/8 or 1/16 duty (for S1D15202) can be
selected by the Duty Select command. If the 1/32 duty is
selected for the S1D15200 and 1/16 duty is selected for
the S1D15202, the 1/32 and 1/16 duties are provided by
two chips consisting of the master and slave chips in the
common multi-chip mode.
S1D15200
S1D15220
(8) Display Data Latch Circuit
This latch stores one line of display data for use by the
LCD driver interface circuitry. The output of this latch
is controlled by the Display ON/OFF and Static Drive
ON/OFF commands.
(9) LCD Driver Circuit
The LCD driver circuitry generates the 80 4-level signals
used to drive the LCD panel, using output from the
display data latch and the common timing generator
circuitry.
2–10
FR signal
(Master output)
Master Common
Slave Common
FR signal
(Master output)
Master Common
Slave Common
0
0
1
1
2
2
14 15
6
7
EPSON
16 17
8
9
(10) Display Timing Generator
This circuit generates the internal display timing signal
using the basic clock, CL, and the frame signals, FR.
FR is used to generate the dual frame AC-drive wave-
form (type B drive) and to lock the line counter and
common timing generator to the system frame rate.
CL is used to lock the line counter to the system line scan
rate. If a system uses both S1D15200 or S1D15202 and
S1D15201 they must have the same CL frequency rating.
30 31
14 15
0
0
1
1
15
7
16 17
8
9
31
15
Rev. 1.1
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