S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 216

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

7. FUNCTIONAL DESCRIPTION
Microprocessor Interface
Parallel/serial interface
Parallel data can be transferred in either direction be-
tween the controlling microprocessor and the S1D15600/
601/602 series through the 8-bit I/O buffer (D0 to D7).
Serial data can be sent from the microprocessor to the
S1D15600/601/602
Note
“—” indicates fixed to either HIGH or to LOW
For the parallel interface, the type of microprocessor is
selected by C86 as shown in table 2.
Parallel interface
A0, WR (or R/W) and RD (or E) identify the type of
parallel data transfer to be made as shown in table 3.
Serial interface
The serial interface comprises an 8-bit shift register and
a 3-bit counter. These are reset when CS1 is HIGH and
CS2 is LOW. When these states are reversed, serial data
and clock pulses can be received from the microproces-
sor on SI and SCL, respectively.
Rev. 4.6
HIGH
HIGH
LOW
LOW
Table 2. Microprocessor selection for parallel
C86
P/S
6800-series CS1 CS2
8080-series CS1 CS2
MPU bus
type
Input type
interface
Parallel
Serial
CS1 CS2
CS1
CS1
CS1
A0
A0
A0
RD
RD
E
CS2
CS2
CS2
Table 1. Parallel/serial interface selection
R/W D0 to D7
WR D0 to D7
WR D0 to D7
A0
A0
A0
EPSON
RD
RD
—
series through the serial data input (SI), but not from the
S1D15600/601/602 series to the microprocessor. The
parallel or serial interface is selected by P/S as shown in
table 1.
Serial data is read on the rising edge of SCL and must be
input at SI in the sequence D7 to D0. On every eighth
clock pulse, the data is transferred from the shift register
and processed as 8-bit parallel data.
Input data is display data when A0 is HIGH and control
data when A0 is LOW. A0 is read on the rising edge of
every eighth clock signal.
The SLC signal is affected by the termination reflection
and external noise caused by the line length. The opera-
tion check on the actual machine is recommended.
Common 6800 series
A0
1
1
0
0
WR
WR
—
R/W
1
0
1
0
Table 3. Parallel data transfer
C86
C86
—
E
1
1
1
1
8080 series
S1D15600/601/602 Series
RD
0
1
0
1
—
SI
SI
WR
1
0
1
0
SCL
SCL
Display data read out
Display data write
Status read
Write to internal reigister
(command)
—
Description
D0 to D7
D0 to D7
(Hz)
7–21