S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 378

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

Serial interface
When the serial interface is selected (P/S=LOW), the
serial data entry (SI) and serial clock input(SCL) can be
accepted with the chip in the non-active state (CS1=LOW
or CS2=HIGH. The serial interface consists of an 8-bit
shift register and a 3-bit counter. Serial data is fetched
from the serial data entry pin in the order of D7, D6, ....,
and D0 on the leading edge of the serial clock and
• When the chip is in the non-active state, both the shift register and counter are reset to the initial state.
• Cannot be read for the serial interface.
• For the SCL signal, pay careful attention to the terminating reflection of lines and external noise. The operation
Chip select
The S1D15705 series has two chip select pins CS1 and
CS2 and enables the MPU interface or serial interface
only when CS1=LOW and CS2=HIGH.
When Chip Select is in the non-active state, D0 to D7 are
in the high impedance state and the A0, RD, and WR
inputs become invalid. When the serial interface is
selected, the shift register and counter are reset.
Display data RAM and internal register
Since the S1D15705 series access viewed from the
MUP side satisfies the cycle time and does not require
the wait time, high-speed data transfer is enabled.
The S1D15705 series performs a kind of inter-LSI
pipeline processing through the bus holder attached to
the internal data bus when it performs the data transfer
with the MPU.
For example, when data is written on the display data
RAM, the data is first held in the bus holder and written
Rev. 3.1a
confirmation using actual equipment is recommended.
access
CS1
CS2
SI
SCL
A0
D7
1
D6
2
D5
3
D4
4
EPSON
D3
5
Fig. 1
D2
6
converted into 8-bit parallel data on the leading edge of
the 8th serial clock, then processed.
Whether to identify that the serial data entry is display
data or command is judged by the A0 input, and
A0=HIGH indicates display data and A0=LOW indicates
the command. After the chip is set to the non-active
state, the A0 input is read and identified at the timing on
the 8 n-th leading edge of the serial clock. Fig. 1 shows
the signal chart of the serial interface.
on the display data RAM up to the next data write cycle.
Further, when the MPU reads the contents of display
data RAM, the read data at the first data read cycle
(dummy) is held in the bus holder and read on the system
bus from the bus holder up to the next data read cycle.
The read sequence of the display data RAM is restricted.
When the address is set, note that the specified address
data is not output to the subsequent read instruction and
output at the second data read. Therefore single dummy
read is required after the address set and write cycle.
Fig. 2 shows this relationship.
Busy flag
When the busy flag is “1”, it indicates that the S1D15705
series is performing an internal operation, and only the
status read instruction can be accepted. The busy flag is
output to the D7 pin using the status read command. If
the cycle time (t
can be improved greatly since this flag needs not be
checked before each command.
D1
7
D0
8
D7
9
CYC
D6
10
) is ensured, the MPU throughput
D5
11
D4
12
S1D15705 Series
D3
13
D2
14
10–19