S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 514

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

* When the chip is inactive, the shift register and the counter is reset to the initial state.
* Data read is not available as long as the serial interface is selected.
* Reasonable care must be exercised so that SCL signal may not be exposed undesirable effects resulting from, for
S1D15A06 Series
Chip select input
The MPU interface (either papallel or serial) is enabled
only when CS=LOW.
When the chip select is inactive, D7 to D0 enter a high
impedance state, and A0, RD and WR inputs are disabled.
When the serial interface is selected, the shift register
and the counter are reset.
Access to DDRAM and internal registers
In accessing the DDRAM and the internal registers of
the S1D15A06 series,the MPU is required to satisfy the
only cycle time (t
wait time. Accordingly, it is possible to transfer data at
higher speed.
In order to realize the higher speed accessing, the
12–10
instance, terminal reflection of wiring or external noises. Before using the signal, it is recommended to test the signal
in actual system.
MPU
Internal Timing
MPU
Internal Timing
CS
SI
SCL
A0
CYC
BUS Holder
Write Signal
Adsress Preset
Read Signal
Column Adsress
Write Signal
),and is not needed to consider the
WR
Data
WR
RD
Data
D7
1
N
N
Address Set
D6
2
#n
Latch
D5
N
3
Preset
D4
4
EPSON
Figure 2
Figure 1
D3
Write
Read
N
N
5
N+1
N
D2
Dummy
6
Read
S1D15A06 series can perform a type of pipeline
processing between LSIs using bus holder of internal
data bus when data is sent from/to the MPU. For
example, when the MPU writes data to the DDRAM,
once the data is stored in the bus holder, then it is written
to the DDRAM before the next data write cycle. And
when the MPU reads the contents of the DDRAM, the
first data read cycle (dummy read cycle) stores the read
data in the bus holder, and then the data is read from the
bus holder to the system bus at the next data read cycle.
Thus,there is a certain restriction in the DDRAM read
sequence. When an address is set, the specified address
data is NOT output at the immediately following read
instruction. The address data is output during second
data read. A single dummy read must be inserted after
address setup and after write cycle (refer to Figure 2).
N+1
D1
7
Increment
D0
8
D7
n
9
N+2
N+1
n
Data Read
D6
10
#n
N+2
D5
11
D4
12
n+1
N+2
D3
13
N+3
n+1
Data Read
#n+1
D2
14
N+3
n+2
Rev. 1.0a