S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 276

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

System Bus Connection Terminals
Rev. 2.4a
Pin Name
D7 to D0
(SI)
(SCL)
A0
RES
CS1
CS2
RD
(E)
WR
(R/W)
C86
P/S
CLS
I/O
I/O
I
I
I
I
I
I
I
I
This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit
standard MPU data bus.
When the serial interface is selected (P/S = LOW), then D7 serves as the
serial data input terminal (SI) and D6 serves as the serial clock input
terminal (SCL). At this time, D0 to D5 are set to high impedance.
When the chip select is inactive, D0 to D7 are set to high impedance.
This is connect to the least significant bit of the normal MPU address bus,
and it determines whether the data bits are data or a command.
A0 = HIGH: Indicates that D0 to D7 are display data.
A0 = LOW: Indicates that D0 to D7 are display control data.
When RES is set to LOW, the settings are initialized.
The reset operation is performed by the RES signal level.
This is the chip select signal. When CS1 = LOW and CS2 = HIGH, then the
chip select becomes active, and data/command I/O is enabled.
• When connected to an 8080 MPU, this is active LOW.
• When connected to a 6800 Series MPU, this is active HIGH.
• When connected to an 8080 MPU, this is active LOW.
• When connected to a 6800 Series MPU:
This is the MPU interface switch terminal.
This is the parallel data input/serial data input switch terminal.
P/S = HIGH: Parallel data input.
P/S = LOW: Serial data input.
The following applies depending on the P/S status:
When P/S = LOW, D0 to D5 are HZ. D0 to D5 may be HIGH, LOW or Open.
RD (E) and WR (P/W) are fixed to either HGIH or LOW.
With serial data input, RAM display data reading is not supported.
Terminal to select whether or enable or disable the display clock internal
oscillator circuit.
When CLS = LOW, input the display clock through the CL terminal.
When using the S1D15605 Series as a master or slave, set respective
CLS pins at the same level.
HIGH
LOW
Display clock
Built-in oscillator circuit used
External input
P/S
This pin is connected to the RD signal of the 8080 MPU, and the
S1D15605 series data bus is in an output status when this signal is LOW.
This is the 6800 Series MPU enable clock input terminal.
This terminal connects to the 8080 MPU WR signal. The signals on
the data bus are latched at the rising edge of the WR signal.
This is the read/write control signal input terminal.
When R/W = HIGH: Read.
When R/W = LOW: Write.
C86 = HIGH: 6800 Series MPU interface.
C86 = LOW: 8080 MPU interface.
CLS = HIGH: Internal oscillator circuit is enabled
CLS = LOW: Internal oscillator circuit is disabled (requires external input)
Data/Command
A0
A0
EPSON
D0 to D7
SI (D7)
Data
Function
Master
HIGH
LOW
Read/Write Serial Clock
Write only
RD, WR
Slave
HIGH
LOW
SCL (D6)
S1D15605 Series
No. of
Pins
8–21
8
1
1
2
1
1
1
1
1