S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 282

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

Display Data RAM
Display Data RAM
The display data RAM is a RAM that stores the dot data
for the display. It has a 65 (8 page
structure. It is possible to access the desired bit by
specifying the page address and the column address.
Because, as is shown in Figure 3, the D7 to D0 display
data from the MPU corresponds to the liquid crystal
display common direction, there are few constraints at
The Page Address Circuit
As shown in Figure 6-4, page address of the display data
RAM is specified through the Page Address Set
Command. The page address must be specified again
when changing pages to perform access.
Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page
for the RAM region used only by the indicators, and
only display data D0 is used.
The Column Addresses
As is shown in Figure 4, the display data RAM column
address is specified by the Column Address Set
command. The specified column address is incremented
(+1) with each display data read/write command. This
allows the MPU display data to be accessed continuously.
Moreover, the incrementation of column addresses stops
with 83H. Because the column address is independent
of the page address, when moving, for example, from
page 0 column 83H to page 1 column 00H, it is necessary
to respecify both the page address and the column
address.
Furthermore, as is shown in Table 4, the ADC command
(segment driver direction select command) can be used
to reverse the relationship between the display data
RAM column address and the segment output. Because
of this, the constraints on the IC layout when the LCD
module is assembled can be minimized.
Rev. 2.4a
D0
D1
D2
D3
D4
—
Display data RAM
0
1
0
0
1
1
0
0
1
0
1
0
0
1
0
8 bit +1) 132 bit
1
0
0
1
0
0
0
0
0
0
EPSON
Figure 3
the time of display data transfer when multiple S1D15605
series chips are used, thus and display structures can be
created easily and with a high degree of freedom.
Moreover, reading from and writing to the display
RAM from the MPU side is performed through the I/O
buffer, which is an independent operation from signal
reading for the liquid crystal driver. Consequently, even
if the display data RAM is accessed asynchronously
during liquid crystal display, it will not cause adverse
effects on the display (such as flickering).
The Line Address Circuit
The line address circuit, as shown in Table 4, specifies
the line address relating to the COM output when the
contents of the display data RAM are displayed. Using
the display start line address set command, what is
normally the top line of the display can be specified (this
is the COM0 output when the common output mode is
normal, and the COM63 output for S1D15605 Series,
COM47 output for S1D15606 Series, COM31 output for
the S1D15607 Series, COM53 output for S1D15608
and COM51 output for S1D15609
output mode is reversed. The display area is a 65 line area
for the S1D15605 Series, a 49 line are for the S1D15606,
a 33 line area for the S1D15607 Series , 55 line area for
the S1D15608
S1D15609
If the line addresses are changed dynamically using the
display start line address set command, screen scrolling,
page swapping, etc. can be performed.
SEG
Output
ADC “0” 0 (H)
(D0) “1” 83 (H)
COM0
COM1
COM2
COM3
COM4
—
*****
Liquid crystal display
SEG0
*****
from the display start line address.
Table 4
Column Address
Column Address
and 53 line area for the
*****
S1D15605 Series
) when the common
SEG 131
83 (H)
0 (H)
*****
8–27