S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 452

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

S1D15710 Series
Display Data RAM
Display data RAM
This display data RAM stores display dot data and
consists of 65 (8 pages
Desired bits can be accessed by specifying page and
column addresses.
Since the MPU display data D7 to D0 correspond to the
common direction of the liquid crystal display, the
restrictions at display data transfer is reduced and the
Page address circuit
As shown in Figure 4, the page address of the display
data RAM is specified using the page address set
command. To access the data using a new page, the page
address is respecified.
The page address 8 (D3,D2,D1,D0=1,0,0,0) is an
indicator dedicated RAM area and only the display data
D0 is valid.
Column address circuit
As shown in Figure 4, the display data RAM column
address is specified by the Column Address Set
command. The specified column address is incremented
by +1 at every input of display data read/write command.
This allows the MPU to access the display data
continuously.
Incrementation of the column address is stopped by
FFH. When display data is accessed continuously, the
column address continues to specify the FFH after
access of the FFH. It should be noted that the column
address FFH display data is accessed repeatedly. The
column address and page address are independent of
each other. Therefore, when shifting from the column
of page 0 to the column of page 1, for example, it is
necessary to specify each of the page address and
column address again.
11–14
D0
D1
D2
D3
D4
—
one 8 bit + 1)
0
1
0
0
1
Display data RAM
1
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
256 bits.
EPSON
Figure 3
display configuration with the high degree of freedom
can easily be obtained when the S1D15710 series is
used for the multiple chip configuration.
Besides, the read/write operation to the display data
RAM is performed through the I/O buffer from the
MPU side independently of the liquid crystal drive
signal read. Therefore even when the display data RAM
is asynchronously accessed during liquid crystal display,
the access will not have any adverse effect on the
display such as flickering.
Furthermore, as shown in Table 4, the AD command
(segment driver direction select command) can used to
reverse the correspondence between the display data
RAM column address and segment output. This allows
constraints on IC layout to be minimized at the time of
LCD module assembling.
Line address circuit
When displaying contents of the display data RAM, the
line address circuit is used for specifying the
corresponding addresses. See Figure 4. Using the
display start line address set command, the top line is
normally selected (when the common output state is
normal, COM0 is output. And, when reversed outputs
COM63). For the display area of 65 lines is secured
starting from the specified display start line address in
the address incrementing direction.
Dynamically changing the line address using the display
start line address set command enables screen scrolling
and page change.
SEG output
ADC
(D0)
COM0
COM1
COM2
COM3
COM4
—
“0”
“1”
Liquid crystal display
FF (H) Column Address
0 (H)
SEG0
Table 4
Column Address
SEG223
Rev. 1.1a
DF (H)
20 (H)