S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 564

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

* When the chip is not active, the shift registers and the counter are reset to their states.
* Reading is not possible while in serial interface mode.
* Caution is required on the SCL signal when it comes to line-end reflections and external noise.
Chip select input
The MPU interface (either parallel or serial) is enabled
only when CS=LOW.
When the chip select is inactive, D7 to D0 enter a high
impedance state, and A0, RD and WR inputs are disabled.
When the serial interface is selected, the shift register
and the counter are reset.
Access to DDRAM and internal registers
In accessing the DDRAM and the internal registers of
the S1D15B01 series, the MPU is required to satisfy the
only cycle time (t
wait time. Accordingly, it is possible to transfer data at
higher speed.
Rev. 1.1a
We recommend that operation be rechecked on the actual equipment.
CS
SI
SCL
A0
WR
DATA
BUS Holder
Write Signal
WR
RD
DATA
Address Preset
Read Signal
Column Address
Bus Holder
CYC
), and is not needed to consider the
D7
1
N
Address Set
N
D6
2
Latch
#n
N
D5
3
D4
Preset N
4
N
D3
EPSON
5
Figure 2
Figure 1
N+1
Write
Read
N
Dummy
D2
Read
6
N+1
In order to realize the higher speed accessing, the
S1D15B01 series can perform a type of pipeline
processing between LSIs using bus holder of internal
data bus when data is sent from/to the MPU. For
example, when the MPU writes data to the DDRAM,
once the data is stored in the bus holder, then it is written
to the DDRAM before the next data write cycle. And
when the MPU reads the contents of the DDRAM, the
first data read cycle (dummy read cycle) stores the read
data in the bus holder, and then the data is read from the
bus holder to the system bus at the next data read cycle.
Thus, there is a certain restriction in the DDRAM read
sequence. When an address is set, the specified address
data is NOT output at the immediately following read
instruction. The address data is output during second
data read. A single dummy read must be inserted after
address setup and after write cycle (refer to Figure 2).
D1
7
D0
8
Increment N+1
n
D7
9
N+2
Data Read
n
D6
10
#n
N+2
D5
11
D4
n+1
12
D3
N+2
S1D15B01 Series
13
N+3
Data Read
n+1
#n+1
D2
14
N+3
n+2
13–9