S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 17

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

A single 4-bit word can be written to memory using the
Data Memory Write command as shown in the following
figure. The lower four bits are stored at the location
specified by the address counter. The address counter is
automatically incremented by one.
Address Counter
Address Decoder
The address decoder sets addresses 0 to 31 of the display
data memory where the display data of address counter
is written.
Rev. 1.0
The address counter is a presettable type to give 5-bit
addresses to the display data memory.
In case of S1D15100 Serise, any address can be set
when the address set command is used.
In case of S1D15100 Serise, set addresses are
automatically incremented by 2 when an 8-bit display
data is stored (C/D = LOW level), or incremented by
1 when a 4-bit data is stored by the display data
memory rewrite command.
The address decoder, after counting Address 31, counts
0 at the next counting and repeats as follows:
1
0
Address 0
Bit 3
D3
0
Address = n
COM0
COM1
COM2
COM3
D2
D3
D1
SEG SEG SEG SEG SEG SEG SEG SEG
Bit 0
D2
D0
0
0
Address 31
1
1
D1
2
2
D0
3
3
4
4
5
5
EPSON
Address
6
6
7
7
Note
Timing Generator
A low-power oscillator can be constructed using an
external feedback resistor as shown in the following
figure.
Alternatively, an 18 kHz external clock can be input on
OSC1, and OSC2 left open, as shown in the following
figure.
Common Counter
The timing generator clock signal is frequency-divided
by the common counter to generate both the common
drive timing and the alternating frame timing.
= don’t care
The display data memory address is automatically
incremented by 2 when a 8-bit display data (C/D =
LOW level) is stored, or incremented by 1 when a 4-
bit data is stored by the display data re-write command.
After the display data is written in the RAM, the RAM
address is held as shown below unless the address is
reset:
After writing a 8-bit display data ...
After rewriting a 4-bit display data ...
Data in the display data memory synchronizes with the
COM0 to COM3 signals and is output in 32 bits to the
segment driver.
The relations of the display data memory, the segment
terminal and common signal selection timing are as
follows:
the final write address is incremented by 2.
the final rewrite address is incremented by 1.
SEG SEG SEG
29
29
30
30
OSC1
External clock
OSC1
31
31
0
1
2
3
680 k
R
Bit
f
Open
S1D15100 Series
OSC2
OSC2
1–5