S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 156

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

S1D15300 Series
AC Characteristics
(1) System buses
Notes: 1. The input signal rise/fall time (t
5–32
Address hold time
Address setup time
System cycle time
Control LOW pulse width(WR)
Control LOW pulse width(RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Address hold time
Address setup time
System cycle time
Control LOW pulse width (WR)
Control LOW pulse width (RD)
Control HIGH pulse width (WR)
Control HIGH pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
2. Every timing is specified on the basis of 20% and 80% of V
3.
4. When it is expected that Vss ranges from -2.4 V to -4.5 V during the operation, increase all the above specifications from -2.7 V to
Parameter
Parameter
When system cycle time is used at a high speed, it is specified by t
t
-4.5 V by 30% before the operation.
t
EWHR
r
+ t
A0
CS1
(CS2="1")
WR,RD
D0~D7
(WRITE)
D0~D7
(READ)
f
and
(
t
CYC8
t
EWHW
-
t
CCLR
are specified by the overlap period in which CS1 is “0” (CS2 = “1”) and WR and RD are “0”.
-
t
CCHR
t
D0 to D7
D0 to D7
AW8
Signal
Signal
).
r
, t
WR
WR
WR
WR
RD
RD
RD
RD
A0
A0
f
) is specified at 15 ns or less.
t
ACC8
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AHIGH8
AW8
CYC8
CCLOWW
CCLOWR
CCHIGHW
CCHIGHR
DS8
DHIGH8
ACC8
CHIGH8
AH8
AW8
CYC8
CCLW
CCLR
CCHW
CCHR
DS8
DH8
ACC8
CH8
t
t
CCLW
CCLR
EPSON
t
DS8
DD
.
Condition
CL=100pF
Condition
CL=100pF
r
+ t
f
t
t
Read/write characteristics I (8080-series microprocessor)
t
CYC8
AH8
t
DH8
CH8
(
t
CYC8
-
t
t
CCHW
CCHR
t
CCLW
V
Min.
166
100
Min.
450
140
200
140
DD
V
10
10
30
70
70
20
10
10
19
15
60
40
15
10
–
–
DD
) or
= 2.7 V to 4.5 V, Ta = –40 to +85 C
= 5.0 V 10%, Ta = –40 to +85 C
Max.
Max.
140
100
70
50
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Rev.1.4
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns