S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 31
![no-image](/images/no-image-200.jpg)
S1D1
Manufacturer Part Number
S1D1
Description
LCD Controller-driver With Built-in Character ROM
Manufacturer
Epson Electronics America, Inc.
Datasheet
1.S1D1.pdf
(612 pages)
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S1D15200 Series
6. PIN DESCRIPTION
(1) Power Supply Pins
(2) System Bus Connection Pins
2–6
V
1
, V
R/W (WR)
D7 to D0
E (RD)
2
Name
, V
RES
V
V
CS
A0
DD
SS
3
, V
4
, V
5
Connected to the +5Vdc power. Common to the V
0 Vdc pin connected to the system ground.
Multi-level power supplies for LCD driving. The voltage determined for each liquid
crystal cell is divided by resistance or it is converted in impedance by the op amp,
and supplied. These voltages must satisfy the following:
V
Three-state I/O.
The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU
data buses.
Input.
Usually connected to the low-order bit of the MPU address bus and used to identify
the data or a command.
Input.
When the RES signal goes
goes
sense of the RES signal. The interface type to the 68-series or 80-series MPU is
selected by the level input as follows:
Input. Active low. Effective for an external clock operation model only.
An address bus signal is usually decoded by use of chip select signal, and it is
entered. If the system has a built-in oscillator, this is used as an input pin to the
oscillator amp and an Rf oscillator resistor is connected to it. In such case, the RD,
WR and E signals must be ORed with the CS signals and entered.
• If the 68-series MPU is connected:
• If the 80-series MPU is connected:
• If the 68-series MPU is connected:
• If the 80-series MPU is connected:
DD
Input. Active HIGH.
Used as an enable clock input of the 68-series MPU.
Input. Active LOW.
The RD signal of the 80-series MPU is entered in this pin. When this signal is
kept low, the SED1520 data bus is in the output status.
Input.
Used as an input pin of read control signals (if R/W is HIGH) or write control
signals (if LOW).
Input. Active LOW.
The WR signal of the 80-series MPU is entered in this pin. A signal on the data
bus is fetched at the rising edge of WR signal.
A0=0: D0 to D7 are display control data.
A0=1: D0 to D7 are display data.
High level: 68-series MPU interface
Low level: 80-series MPU interface
V
1
V
, the 80-series MPU is initialized. The system is reset during edge
2
V
3
V
4
V
EPSON
5
the 68-series MPU is initialized, and when it
Description
CC
MPU power pin.
Rev. 1.1
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