S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 515

• Manufacturer Part Number: S1D1
• Description: LCD Controller-driver With Built-in Character ROM
• Manufacturer: Epson Electronics America, Inc.

DDRAM
DDRAM and page/column address circuit
The DDRAM stores pixel data for LCD. It is a 65-row
(8 page by 8 bit + 1) by 102-column addressable array.
As is shown in Figure 3, the D7 to D0 display data from
the MPU corresponds to the LCD common direction.
Moreover, reading from and writing to the display
RAM from the MPU side is performed through the I/O
Rev. 1.0a
Page address circuit
Each pixel can be selected when page address and
column address are specified(refer to Figure 5).
The MPU issues Page address set command to change
the page and access to another page. Page address 8
(D3,D2,D1,D0 = 1,0,0,0) is DDRAM area dedicate to
the indicator, and display data D0 is only valid.
The DDRAM column address is specified by Column
address set command.The specified column address is
Page address
Data
D0
D1
D2
D3
D4
D5
D6
D7
0H
1H
2H
3H
4H
5H
6H
7H
8H
D0
D1
D2
D3
D4
—
0
102
204
306
408
510
612
714
00H
0
1
0
0
1
1
0
0
1
0
1
103
205
307
409
511
613
715
01H
DDRAM
1
0
0
1
0
1
0
0
1
0
2
104
206
308
410
512
614
716
02H
0
0
0
0
0
EPSON
Figure 4
Figure 3
Column address
buffer, which is an independent operation from signal
reading for the liquid crystal driver. Consequently,
even if the display data RAM is accessed asynchronously
during liquid crystal display, it will not cause adverse
effects on the display (such as flickering).
automatically incremented by +1 when a Display data
read/write command is entered. After the last column
address (65H) ,column address returns to 00H and page
address incremented by +1 (refer to Figure 4). After the
very last address (column = 65H,page = 7H),both column
address and page address return to 00H (column address
= 00H, page address = 0H).
COM0
COM1
COM2
COM3
COM4
—
Display on LCD
100
202
304
406
508
610
712
814
64H
101
203
305
407
509
611
713
815
65H
S1D15A06 Series
12–11