S1D1 Epson Electronics America, Inc., S1D1 Datasheet - Page 72

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S1D1

Manufacturer Part Number
S1D1
Description
LCD Controller-driver With Built-in Character ROM
Manufacturer
Epson Electronics America, Inc.
Datasheet

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S1D15210 Series
(4) Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not
changed continuously.
This command loads the column address register.
(5) Read Status
Reading the command I/O register (A0=0) yields system status information.
• The busy bit indicates whether the driver will accept a command or not.
• The ADC bit indicates the way column addresses are assigned to segment drivers.
• The ON/OFF bit indicates the current status of the display.
• The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.
(6) Write Display Data
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page
address registers and then increments the column address register by one.
3–14
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.
Busy=0: The driver will accept a new command.
ADC=1: Normal. Column address n
ADC=0: Inverted. Column address 79-n
It is the inverse of the polarity of the display ON/OFF command.
ON/OFF=1: Display OFF
ON/OFF=0: Display ON
RESET=1: Currently executing reset command.
RESET=0: Normal operation
A
A
A
0
0
1
0
0
0
RD
RD
RD
(E)
(E)
(E)
1
0
1
(R/W)
(R/W)
R/W
WR
WR
WR
0
1
0
BUSY ADC ON/OFF RESET
A
D
D
D
0
0
1
0
6
7
7
7
A
0
0
0
5
D
D
D
A
A
6
6
6
6
0
0
0
segment driver n.
4
A
segment driver u.
0
0
1
:
:
3
D
A
D
D
5
5
5
5
A
0
0
1
EPSON
2
A
Write data
D
A
D
D
0
0
1
1
4
4
4
4
A
0
1
1
0
D
D
D
A
0
Column Address
3
3
3
3
D
D
D
A
0
79
0
1
2
2
:
:
2
2
D
D
D
A
0
1
1
1
1
D
A
D
D
0
0
0
0
0
00H to 4FH
Rev. 1.1

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