EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 8

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
Table 2-4.
8
Parameter
Input resistance
- Single-ended
- Differential
Clock inputs
Logic common mode compatibility for clock inputs
ADC intrinsic clock jitter
Clock inputs internal DC common mode voltage
Clock input voltage on each single ended input (2.5 GHz
sinewave)
Clock input voltage into 100Ω differential clock input
(2.5 GHz sinewave)
Clock input power level (2.5 GHz low phase noise sinewave
input) in 50Ω
Sinewave or Square wave
Clock signal (minimum) slew-rate
Square Wave differential Clock input voltage on 100Ω input
(LVDS & LVPECL compatible)
Clock input capacitance (die)
Clock input Resistance
- Single-ended
- Differential
Digital Data Outputs
Logic compatibility
50Ω transmission lines, 100Ω (2 × 50Ω) differential
termination
- Logic low
- Logic high
- Differential output
- Common mode
Control Function Inputs
ASYNCRST (DEMUX Reset) input voltages and currents
- Logic Low
- Logic High (reset mode)
DRR (ADC reset)
Logic low
Logic high
Threshold
0954B–BDC–12/09
Electrical Characteristics for Supplies, Inputs and Outputs (Continued)
(2)
(1)
Test Level
4
4
4
4
4
4
4
4
4
4
4
1
1
4
V
|V
SR
CLK
P
R
CLK
Symbol
VODIFF
CLK-CLKN
R
VOCM
CLK, CLKN
CLK, CLKN
CLK, CLKN
VSQ
C
R
VOH
VOL
V
IN, INN
V
R
or V
V
V
V
V
I
–V
I
CLK
CLK
CM
IH
IL
TH
IH
IH
IN
IL
IL
CLKN
CLKN
|
or low jitter LVDS/LVPECL (<100 fs rms)
±0.158
0.632
1.125
–300
0.25
1.25
Min
250
1.8
1.5
47
94
–3
47
94
5
0
0
Low phase noise sinewave
at 2.5 GHz (> 155 dBc/Hz)
±0.25
1.075
1.375
LVDS
1.25
Typ
100
120
100
350
3.0
0.8
0.3
1.4
50
+1
50
1
8
e2v semiconductors SAS 2009
1.375
V
V
±0.5
Max
1.25
106
106
450
1.4
1.1
53
+7
53
50
CCA3
CCD
2
2
fs rms
GV/s
dBm
Unit
Vpp
Vpp
mV
pF
µA
µA
Ω
Ω
V
V
Ω
Ω
V
V
V
V
V
V
V
V