EVX10AS150ATP ETC-unknow, EVX10AS150ATP Datasheet - Page 42

• Manufacturer Part Number: EVX10AS150ATP
• Description: Adc Single 2.5gsps 10-bit Lvds 317-pin Ebga
• Manufacturer: ETC-unknow

EV10AS150A
42
0954B–BDC–12/09
Please refer to
The 3WSI gives a “write-only” access to up to 16 different internal registers of up to 10 bits each.
The input format is fixed with always 4 bits of register address followed by always 10 bits of data.
Address and data are entered MSB first.
The write procedure is fully synchronous with the clock rising edge of SCLK and described in the write
chronogram
For proper initialization of 3WSI default settings, an asynchronous reset pulse on pin RESET is
required.
The RESET pin combined with the SLDN pin must be used as a reset to program the chip to the “reset
setting”.
SLDN and SDATA are sampled on each rising edge of SCLK clock (clock cycle).
SLDN must be set at “1” when no write procedure is done.
A minimum of one clock rising edge (clock cycle) with SLDN at “1” is required for a correct start of the
write procedure.
A write starts on the first clock cycle with SLDN at “0”. SLDN must stay at “0” during the complete write
procedure.
In the first 4 clock cycles with SLDN at “0”, 4 bits of register address from MSB (a[3]) to LSB (a[0]) are
entered.
In the next 10 clock cycles with SLDN at “0”, 10 bits of data from MSB (d[9]) to LSB (d[0]) are entered.
An additional clock cycle with SLDN at “0” is required for parallel transfer of the serial data d[9:0] in the
register addressed with address a[3:0].
This gives 15 clock cycles with SLDN at “0” for a normal write procedure.
A minimum of one clock cycle with SLDN returned at “1” is requested to end the write procedure, before
the interface is ready for a new write procedure.
Any clock cycle with SLDN at “1” before the write procedure is completed, interrupts this procedure and
no data transfer to internal registers is done.
Additional clock cycles with SLDN at “0” after the parallel data transfer to the register (done at 15
secutive clock cycle with SLDN at “0”) do not affect the write procedure and are ignored.
It is possible to have only one clock cycle with SLDN at “1” between two successive write procedures.
10 bits of data must always be entered even if the internal addressed register has less than 10 bits.
Unused bits (usually MSB’s) are ignored. Bit signification and bit position for the internal registers are
detailed in the
• RESET high: no effect
• RESET low and SLDN low: programming of registers to default values
Figure 4-13 on page
Section
Table 2-4 on page 7
4.5.3.
43.
for logical levels of SLCK, SLDN, SDATA and RESET.
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